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參數(shù)資料
| 型號： | M34F04 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | EEPROM |
| 英文描述： | 4Kbit Serial I2C Bus EEPROM With Hardware Write Control on Top Half of Memory |
| 中文描述： | 4Kbit串行I2C總線的EEPROM，帶有硬件寫控制記憶的上半部分 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 262K |
| 代理商： | M34F04 |
7/20
M34F04
DEVICE OPERATION
The device supports the I
2
C protocol. This is sum-
marized in Figure 5. Any device that sends data on
to the bus is defined to be a transmitter, and any
device that reads the data to be a receiver. The
device that controls the data transfer is known as
the bus master, and the other as the slave device.
A data transfer can only be initiated by the bus
master, which will also provide the serial clock for
synchronization. The M24Cxx device is always a
slave in all communication.
Start Condition
Start is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command. The device continuously
monitors (except during a Write cycle) Serial Data
(SDA) and Serial Clock (SCL) for a Start condition,
and will not respond unless one is given.
Stop Condition
Stop is identified by a rising edge of Serial Data
(SDA) while Serial Clock (SCL) is stable and driv-
en High. A Stop condition terminates communica-
tion between the device and the bus master. A
Read command that is followed by NoAck can be
followed by a Stop condition to force the device
into the Stand-by mode. A Stop condition at the
end of a Write command triggers the internal EE-
PROM Write cycle.
Acknowledge Bit (ACK)
The acknowledge bit is used to indicate a success-
ful byte transfer. The bus transmitter, whether it be
bus master or slave device, releases Serial Data
(SDA) after sending eight bits of data. During the
9
th
clock pulse period, the receiver pulls Serial
Data (SDA) Low to acknowledge the receipt of the
eight data bits.
Data Input
During data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
Clock (SCL), and the Serial Data (SDA) signal
must change
only
when Serial Clock (SCL) is driv-
en Low.
Memory Addressing
To start communication between the bus master
and the slave device, the bus master must initiate
a Start condition. Following this, the bus master
sends the Device Select Code, shown in Table 2
(on Serial Data (SDA), most significant bit first).
The Device Select Code consists of a 4-bit Device
Type Identifier, and a 2-bit Chip Enable “Address”
(E2, E1). To address the memory array, the 4-bit
Device Type Identifier is 1010b.
When the Device Select Code is received on Seri-
al Data (SDA), the device only responds if the Chip
Enable Address is the same as the value on the
Chip Enable (E1, E2) inputs.
The 8
th
bit is the Read/Write bit (RW). This bit is
set to 1 for Read and 0 for Write operations.
If a match occurs on the Device Select code, the
corresponding device gives an acknowledgment
on Serial Data (SDA) during the 9
th
bit time. If the
device does not match the Device Select code, it
deselects itself from the bus, and goes into Stand-
by mode.
Using the E1 and E2 inputs pins, up to four
M34F04 devices can be connected to one I
2
C bus.
Table 3. Operating Modes
Note: 1. Z = unconnected and floating
X =
V
IH
or V
IL
or unconnected and floating.
Mode
RW bit
WC
1
Bytes
Initial Sequence
Current Address Read
1
X
1
START, Device Select, RW = 1
Random Address Read
0
X
1
START, Device Select, RW = 0, Address
1
X
reSTART, Device Select, RW = 1
Sequential Read
1
X
≥
1
Similar to Current or Random Address Read
Byte Write (upper addresses)
0
V
IL
or Z
1
START, Device Select, RW = 0
Byte Write (lower addresses)
0
X
1
START, Device Select, RW = 0
Page Write (upper addresses)
0
V
IL
or Z
≤
16
START, Device Select, RW = 0
Page Write (lower addresses)
0
X
≤
16
START, Device Select, RW = 0
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