參數(shù)資料
型號: M34F04-WMN6TG
廠商: 意法半導(dǎo)體
元件分類: DRAM
英文描述: 4Kbit Serial I2C Bus EEPROM With Hardware Write Control on Top Half of Memory
中文描述: 4Kbit串行I2C總線的EEPROM,帶有硬件寫控制記憶的上半部分
文件頁數(shù): 15/20頁
文件大小: 262K
代理商: M34F04-WMN6TG
15/20
M34F04
Table 8. DC Characteristics
Table 9. AC Characteristics
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
Symbol
Parameter
Test Condition
(in addition to those in Table 5)
Min.
Max.
Unit
I
LI
Input Leakage Current
(SCL, SDA)
V
IN
= V
SS
or
V
CC
± 2
μA
I
LO
Output Leakage Current
V
OUT
= V
SS
or
V
CC,
SDA in Hi-Z
± 2
μA
I
CC
Supply Current
V
CC
=2.5V, f
c
=400kHz (rise/fall time < 30ns)
1
mA
I
CC1
Stand-by Supply Current
V
IN
= V
SS
or
V
CC
, V
CC
= 2.5 V
0.5
μA
V
IL
Input Low Voltage
(E2, E1, SCL, SDA)
–0.3
0.3V
CC
V
V
IH
Input High Voltage
(E2, E1, SCL, SDA, WC)
0.7V
CC
V
CC
+1
V
V
OL
Output Low Voltage
I
OL
= 2.1 mA, V
CC
= 2.5 V
0.4
V
Test conditions specified in Table 6 and Table 5
Symbol
Alt.
Parameter
Min.
Max.
Unit
f
C
f
SCL
Clock Frequency
400
kHz
t
CHCL
t
HIGH
Clock Pulse Width High
600
ns
t
CLCH
t
LOW
Clock Pulse Width Low
1300
ns
t
DL1DL2 2
t
F
SDA Fall Time
20
300
ns
t
DXCX
t
SU:DAT
Data In Set Up Time
100
ns
t
CLDX
t
HD:DAT
Data In Hold Time
0
ns
t
CLQX
t
DH
Data Out Hold Time
200
ns
t
CLQV 3
t
AA
Clock Low to Next Data Valid (Access Time)
200
900
ns
t
CHDX 1
t
SU:STA
Start Condition Set Up Time
600
ns
t
DLCL
t
HD:STA
Start Condition Hold Time
600
ns
t
CHDH
t
SU:STO
Stop Condition Set Up Time
600
ns
t
DHDL
t
BUF
Time between Stop Condition and Next Start Condition
1300
ns
t
W
t
WR
Write Time
5
ms
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