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參數(shù)資料
| 型號： | M34F04-WMN6TG |
| 廠商： | 意法半導體 |
| 元件分類： | DRAM |
| 英文描述： | 4Kbit Serial I2C Bus EEPROM With Hardware Write Control on Top Half of Memory |
| 中文描述： | 4Kbit串行I2C總線的EEPROM，帶有硬件寫控制記憶的上半部分 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 262K |
| 代理商： | M34F04-WMN6TG |
11/20
M34F04
Figure 9. Read Mode Sequences
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1
st
and 3
rd
bytes) must be identical.
Read Operations
Read operations are performed independently of
the state of the Write Control (WC) signal.
Random Address Read
A dummy Write is performed to load the address
into the address counter (as shown in Figure 9) but
without
sending a Stop condition. Then, the bus
master sends another Start condition, and repeats
the Device Select Code, with the RW bit set to 1.
The device acknowledges this, and outputs the
contents of the addressed byte. The bus master
must
not
acknowledge the byte, and terminates
the transfer with a Stop condition.
Current Address Read
The device has an internal address counter which
is incremented each time a byte is read. For the
Current Address Read operation, following a Start
condition, the bus master only sends a Device Se-
lect Code with the RW bit set to 1. The device ac-
knowledges this, and outputs the byte addressed
by the internal address counter. The counter is
then incremented. The bus master terminates the
transfer with a Stop condition, as shown in Figure
9,
without
acknowledging the byte.
Sequential Read
This operation can be used after a Current Ad-
dress Read or a Random Address Read. The bus
S
DEV SEL *
BYTE ADDR
S
DEV SEL
DATA OUT 1
AI01942
DATA OUT N
S
S
CURRENT
ADDRESS
READ
DEV SEL
DATA OUT
RANDOM
ADDRESS
READ
S
S
DEV SEL *
DATA OUT
SEQUENTIAL
CURRENT
READ
S
DATA OUT N
S
DEV SEL *
BYTE ADDR
SEQUENTIAL
RANDOM
READ
S
DEV SEL *
DATA OUT 1
S
ACK
R/W
NO ACK
ACK
R/W
ACK
ACK
R/W
ACK
ACK
ACK
NO ACK
R/W
NO ACK
ACK
ACK
R/W
ACK
ACK
R/W
ACK
NO ACK
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