參數(shù)資料
型號(hào): M34A08-VDW6T
廠商: 意法半導(dǎo)體
英文描述: 2 Kbit Serial SMBus EEPROM for ACR Card Configuration
中文描述: 2千位串行EEPROM中的SMBus對(duì)于ACR卡配置
文件頁(yè)數(shù): 9/15頁(yè)
文件大小: 123K
代理商: M34A08-VDW6T
9/15
M34A02
Table 5. DC Characteristics
(T
A
= –40 to 85 °C; V
CC
= 2.7 to 3.6 V)
Symbol
Parameter
Table 6. AC Characteristics
Note: 1. For a reStart condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
Test Condition
Min.
Max.
Unit
I
LI
Input Leakage Current
(SCL, SDA, E2, E1, E0)
0 V
V
IN
V
CC
± 2
μA
I
LO
Output Leakage Current
0 V
V
OUT
V
CC,
SDA in Hi-Z
± 2
μA
I
CC
Supply Current
V
CC
=3.6V, f
c
=100kHz (rise/fall time < 30ns)
2
mA
V
CC
=2.7V, f
c
=100kHz (rise/fall time < 30ns)
1
mA
I
CC1
Supply Current (Stand-by)
V
IN
= V
SS
or
V
CC
1
μA
V
IL
Input Low Voltage
(E0-E2, SCL, SDA)
– 0.3
0.8
V
V
IH
Input High Voltage
(E0-E2, SCL, SDA)
2.1
V
CC
+1
V
V
IL
Input Low Voltage (WC)
– 0.3
0.5
V
V
IH
Input High Voltage (WC)
2.1
V
CC
+1
V
V
OL
Output Low Voltage
I
OL
= 3 mA
0.4
V
Symbol
Alt.
Parameter
M34A02
Unit
V
CC
=2.7 to 3.6V
T
A
= –40 to 85°C
Min
Max
t
CH1CH2
t
R
Clock Rise Time
1000
ns
t
CL1CL2
t
F
Clock Fall Time
300
ns
t
DH1DH2 2
t
R
SDA Rise Time
1000
ns
t
DL1DL2 2
t
F
SDA Fall Time
300
ns
t
CHCL
t
HIGH
Clock Pulse Width High
4
μs
t
CLCH
t
LOW
Clock Pulse Width Low
4.7
μs
t
CHDX 1
t
SU:STA
START Set-up Time
4.7
μs
t
DLCL
t
HD:STA
START Hold Time
4
μs
t
DXCX
t
SU:DAT
SDA In Set-up Time
250
ns
t
CLDX
t
HD:DAT
SDA In Hold Time
0
μs
t
CHDH
t
SU:STO
STOP Set-up Time
4
μs
t
DHDL
t
BUF
Time the bus must be free between STOP and next START
4.7
μs
t
CLQV 3
t
AA
Clock Low to SDA Out Valid
400
900
ns
t
CLQX
t
DH
SDA Out Hold Time after Clock Low
300
ns
f
C
f
SCL
Clock Frequency
10
100
kHz
t
W
t
WR
Write Time
10
ms
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