M34A02
2/15
is followed by a Device Select code and RW bit (as
described in Table 3), terminated by an
acknowledge bit.
When writing data to the memory, the device
inserts an acknowledge bit during the 9
th
bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
Power On Reset: V
CC
Lock-Out Write Protect
In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until V
CC
has reached the POR
threshold value, and all operations are disabled –
the device will not respond to any command. In the
same way, when V
CC
drops from the operating
voltage, below the POR threshold value, all
operations are disabled and the device will not
respond to any command. A stable and valid V
CC
must be applied before applying any logic signal.
SIGNAL DESCRIPTION
Serial Clock (SCL)
This input signal is used to strobe all data in and
out of the device. In applications where this line is
used by slave devices to synchronize the bus to a
slower clock, the bus master must have an open
drain output, and a pull-up resistor must be
connected from Serial Clock (SCL) to V
CC
. (Figure
3 indicates how the value of the pull-up resistor
Figure 2. SO and TSSOP Connections
1
2
3
4
AI03795
8
7
6
5
SDA
VSS
SCL
WC
E1
E2
E0
VCC
M34A02
Table 2. Absolute Maximum Ratings
1
Note: 1.
Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality
documents.
2. IPC/JEDEC J-STD-020A
3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500
, R2=500
)
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
–40 to 125
°C
T
STG
Storage Temperature
–65 to 150
°C
T
LEAD
Lead Temperature during
Soldering
SO8: 20 seconds (max)
2
TSSOP8: 20 seconds (max)
2
235
235
°C
V
IO
Input or Output range
–0.6 to 6.5
V
V
CC
Supply Voltage
–0.3 to 6.5
V
V
ESD
Electrostatic Discharge Voltage (Human Body model)
3
4000
V
Figure 3. Typical ACR Application PCB
Connection (showing E2,E1,E0 address 000)
Note: 1. This arrangement on the chip enable lines allows the
application to start at ACR address 000h.
AI04092
E0
E1
E2
VSS
VCC
WC
SCL
SDA
VCC
VSS
ACR Bus
RL