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參數(shù)資料
| 型號： | M3488Q1 |
| 廠商： | 意法半導體 |
| 英文描述： | 256 x 256 DIGITAL SWITCHING MATRIX |
| 中文描述： | 256 × 256數(shù)字切換矩陣 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 193K |
| 代理商： | M3488Q1 |
PIN DESCRIPTION
D7to D0
Databuspins.Thebidirectionalbusis usedto trans-
ferdataandinstructionsto/fromthemicroprocessor.
D0 is theleast significant digit. The outputbus is 8
bits wide ; input is only 5 bits wide. (D4 to D0)
ThebusistristateandcannotbeusedwhileRESET
is held low.
The meaningof input data, suchasbus or channel
numbers,and of expectedoutput data is specified
indetailbytheinstructiondescription.(Pagg.12-14)
C/D (pin 30)
Input control pin, select pin. In a write operation
C/D = 0 qualifies any bus content as data, while
C/D=1 qualifiesitasanopcode.Inareadoperation
OR1 is selected by C/D = 0, OR2 by C/D = 1.
A1,S1, A2, S2
Address select or match pins. In a multi-chip con-
figuration(e.g. asinglestagematrixexpansion),us-
ingthesame CS pins,the matchcondition(A1 = S1
andA2= S2)leavesthecommandinstructionasde-
fined;onthe contrarythe mismatch conditionmodi-
fies the execution as follows : instructions1 and 3
arereversedto channeldisconnection,instruction5
is unaffected,instructions 2-4-6 are cancelled (not
executed).
Bus reading takes place only on match condition,
instructionflow is in any caseaffected.
Eachpinscoupleiscommutative:inamultichipcon-
figurationpinsS1andS2giveahard-wiredaddress
selectionforindividualmatrixes,whileinsingle con-
figuration S1 and A1 or S2 and A2 arenormally
tiedtogether.
CS1, CS2
Commutativechip select pins.They enablethe de-
vice to perform valid read/write operations (active
low). Two pins allow row/column selectionwith dif-
ferent types of microprocessors ; normally one is
tiedto ground.
WR
PinWR, when CS1 andCS2are low, enablesdata
transferfrom microprocessor to thedevice. Dataor
opcodeandcontrolsarelatchedon WR risingedge.
Becauseofinternalclockresynchronizationonesin-
gleadditionalrequirementis recommendedinorder
to producea simultaneousinstruction executionin
amultichip configuration: WR rising edgehas to be
20 to 20 + t
WL(CK)
nsec late relative to clock falling
edge.
RD
WhenCS1andCS2arelowandmatchconditionex-
ists, a low level on RD enablesa register OR1 or
OR2 read operation, throughthe bidirectionalbus.
In addition, the rising edge of RD latches C/D and
the match condition pinsin order to direct the inter-
nal flow of operations. Because of internal clock
resynchronization, one single additional require-
ment is recommended in order to produce a simul-
taneousinstructionflowinamultichip configuration:
theRD rising edgehasto be20 to 20+ t
WL(CK)
nsec
late relative to clock falling edge.
DR
Data ready.Normally high,DR outputpin goeslow
to tell the microprocessorthat :
a) the instruction codewas foundto be invalid ;
b) executing instruction 5 an active outputchannel
was found in the whole matrix array, that is a CM
word not all ”ones” was found in a configurationof
devices sharingthe same CS pins ;
c)executinginstruction6”0channelextraction”took
place and OR2 was loaded with total number of
messagesinserted on 0 timeslot.
DR is active low about two clock cycles in case
b
and
c
;in casea it is left low untila valid instruction
code is supplied.
RESET
RESETcontrol pin is normallyused at the very be-
ginning to initialize the device or the network. Any
logicalstatusis resetandCMissettoall ”ones”after
RESETgoinglow.
The internal initialization routine takes one time
framewhatevertheRESETwidth onlowlevel(mini-
mumonecycleroughly),butitisrepeatedaninteger
numberof time frames as long as RESET is found
low during0 timeslot.
Initializationpulls theinterfacebus immediatelyto a
highimpedancestate.AftertheCM hasbeensetto
all ”ones”the PCM output channelsare also set to
high impedancestate.
CLOCK
Inputmaster clock. Typical frequencyis 4.096MHz.
First division gives an internalclock controlling the
input and output channelsbit rate.
SYNC
Input synchronization signal is active low. Typical
frequencyis 8kHz.
M3488
11/18
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