參數(shù)資料
型號(hào)： M34551M8
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER
中文描述： 單芯片4位CMOS微機(jī)紅外遙控器
文件頁數(shù)： 3/68頁
文件大?。?/td> 698K
代理商： M34551M8
3
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
PERFORMANCE OVERVIEW
Parameter
Number of basic instructions
Minimum instruction execution time
Memory sizes
ROM
Function
92
1.5
μ
s (f(X
IN
) = 8.0 MHz:system clock = f(X
IN
)/4: V
DD
= 5.0 V)
4096 words
10 bits
8192 words
10 bits
280 words
4 bits (LCD RAM 20 words
4 bits included)
Eight independent output ports
4-bit I/O port; each pin is equipped with a pull-up function.
4-bit I/O port; each pin is equipped with a pull-up function.
4-bit input port
1-bit output port (CMOS output)
8-bit timer with a reload register
14-bit timer/
Fixed dividing frequency timer
4-bit timer with a reload register
3 (one for external and two for timer)
1 level
8 levels (however, only 7 levels can be used when an interrupt is used or the TABP p instruction
is executed)
1/2, 1/3 bias
2, 3, 4 duty
4
20
200 k
3
CMOS silicon gate
48-pin plastic molded QFP
–20
°
C to 70
°
C
2.2 V to 5.5 V (One Time PROM version: 2.5 V to 5.5 V)
2.5 mA (f(X
IN
) = 8.0 MHz system clock = f(X
IN
)/4, V
DD
=5 V)
27.5
μ
A (at main clock oscillation stop, sub-clock oscillation frequency: 32.0 kHz, V
DD
=5 V)
0.1
μ
A (at main clock oscillation stop, sub-clock oscillation stop, Ta=25
°
C, V
DD
=5V)
Input/Output
ports
Timers
Interrupt
Subroutine nesting
LCD
Device structure
Package
Operating temperature range
Supply voltage
Power
dissipation
(typical value)
RAM
D
0
–D
7
P0
0
–P0
3
P1
0
–P1
3
P2
0
–P2
3
CARR
Timer 1
Timer 2/
Watchdog timer
Timer LC
Sources
Nesting
Selective bias value
Selective duty value
Common output
Segment output
Internal resistor for
power supply
at active
at clock operating
at RAM back-up
M34551M4
M34551E8
Output
I/O
I/O
Input
Output
DEFINITION OF CLOCK AND CYCLE
G
System clock (STCK)
The system clock is the basic clock for controlling this product.
The system clock can be selected by bits 0 and 3 of the clock
control register MR as shown in the table below.
Table Selection of system clock
Register MR
MR
3
0
0
1
1
1
f(X
CIN
)/4
G
Instruction clock (INSTK)
The instruction clock is the standard clock for controlling CPU.
The instruction clock is a signal derived from dividing the
system clock by 3. The one cycle of the instruction clock is
equivalent to the one machine cycle.
G
Machine cycle
The machine cycle is the standard cycle required to execute
the instruction.
Note: f(X
IN
)/4 is selected immediately after system is released
from reset.
MR
0
0
1
0
System clock (STCK)
f(X
IN
)
f(X
CIN
)
f(X
IN
)/4
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