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參數(shù)資料
| 型號(hào)： | M34551M8 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER |
| 中文描述： | 單芯片4位CMOS微機(jī)紅外遙控器 |
| 文件頁數(shù)： | 15/68頁 |
| 文件大小： | 698K |
| 代理商： | M34551M8 |
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15
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
(6) Interrupt control register
G
Interrupt control register V1
Interrupt enable bits of external 0, timer 1 and timer 2 are
assigned to register V1. Set the contents of this register
through register A with the TV1A instruction. The TAV1
instruction can be used to transfer the contents of register
V1 to register A.
Table 6 Interrupt control register
V1
3
V1
2
V1
1
V1
0
Timer 2 interrupt enable bit
Timer 1 interrupt enable bit
Not used
External 0 interrupt enable bit
0
1
0
1
0
1
0
1
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
Interrupt control register V1
at reset : 0000
2
at power down : 0000
2
R/W
Note: “R” represents read enabled, and “W” represents write enabled.
(7) Interrupt sequence
Interrupts occur only when the respective INTE flag, interrupt
enable bits (V1
0
–V1
3
), and interrupt request flags (EXF0, T1F,
T2F) are “1.” The interrupt actually occurs 2 to 3 machine
cycles after the cycle in which all three conditions are satisfied.
The interrupt occurs after 3 machine cycles only when the
three interrupt conditions are satisfied on execution of other
than one-cycle instructions (Refer to Figure 16).
Fig. 16 Interrupt sequence
The address is stacked to the last cycle.
This interval of cycles depends on the executed instruction at the time when each interrupt activated
condition is satisfied.
2 to 3 machine cycles
(Note 1, 2)
Software starts from the
interrupt address.
Flag cleared
Interrupt enabled state
EI instruction
execution cycle
Interrupt enable
flag (INTE)
Retaining level for 4 cycles or
more of STCK is necessary.
Interrupt disabled state
EXF0
flag
T1F, T2F
flags
INT pin
External
interrupt
Timer 1
and
Timer 2
interrupts
Interrupt activated
condition is satisfied.
G
When an interrupt request flag is set after its interrupt is enabled
1 machine cycle
System clock (STCK)
“H”
“L”
“1”
“0”
“1”
“0”
“1”
“0”
Notes 1:
2:
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