參數(shù)資料
型號： M34551M8
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER
中文描述： 單芯片4位CMOS微機紅外遙控器
文件頁數(shù)： 21/68頁
文件大?。?/td> 698K
代理商： M34551M8
21
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
(2) Precautions
Note the following for the use of timers.
G
Prescaler
Stop the prescaler operation to change its frequency
dividing ratio.
G
Count source
Stop timer 1 or timer LC counting to change its count
source. When timer 2 count source changes from f(X
CIN
)
to ORCLK (W2
3
= “0”
→
W2
3
= “1”), the count value of
timer 2 is initialized. However, when timer 2 count source
changes from ORCLK to f(X
CIN
) (W2
3
= “1”
→
W2
3
= “0”)
or the same count source is set again (W2
3
= “0”
→
W2
3
= “0” or W2
3
= “1”
→
W2
3
= “1”), the count value of timer
2 is not initialized.
G
Timer 2
Timer 2 has the watchdog timer function (WDT). When
timer 2 is used as the WDT, note that the processing to
initialize the count value and the execution of the WRST
instruction.
G
Reading the count value
Stop the prescaler and then execute the TAB1 instruction
to read timer 1 data.
G
Writing to reload register R1
When writing data to reload register R1 while timer 1 is
operating, avoid a timing when timer 1 underflows.
(3) Prescaler
Prescaler is a frequency divider. Its frequency dividing ratio
can be selected. The count source of prescaler is the
instruction clock (INSTCK).
Use the bit 2 of register W1 to select the prescaler dividing
ratio and the bit 3 to start and stop its operation. When the bit
3 of register W1 is cleared to “0,” prescaler is initialized, and
the output signal (ORCLK) stops.
(4) Timer 1 (interrupt function)
Timer 1 is an 8-bit binary down counter with the timer 1 reload
register (R1). When timer 1 stops, data can be set
simultaneously in timer 1 and the reload register (R1) with
the T1AB instruction. When timer 1 is operating, data can be
set only in the reload register (R1) with the T1AB instruction.
When setting the next count data to reload register R1 while
timer 1 is operating, be sure to set data before timer 1
underflows.
Timer 1 starts counting after the following process;
set data in timer 1,
select the count source with bits 0 and 1 of register W1,
set the bit 0 of register W2 to “1.”
Once count is started, when timer 1 underflows (the next count
pulse is input after the contents of timer 1 becomes “0”), the
timer 1 interrupt request flag (T1F) is set to “1,” new data is
loaded from reload register R1, and count continues (auto-
reload function).
When a value set in reload register R1 is n, timer 1 divides
the count source signal by n + 1 (n = 0 to 255).
Data can be read from timer 1 to registers A and B. Stop
counting and then execute the TAB1 instruction to read its
data.
(5) Timer 2 (interrupt function)
Timer 2 is a 14-bit binary down counter.
Timer 2 starts counting after the following process;
select the count source with the bit 3 of register W2, and
the clock as a count source is supplied.
Timer 2 stops counting and its count value is retained when
supply of a clock as a count source stops. Timer 2 is initialized
at reset and when the count source changes from f(X
CIN
)
(W2
3
=“0”) to ORCLK (W2
3
=“1”).
The count value to set the timer 2 interrupt request flag (T2F)
to “1” can be selected from every 8192 count or every 16384
count with bits 1 and 2 of register W2. The count source signal
divided by 16 is output from timer 2.
Timer 2 can be used as a counter for clock in the clock
operating mode (POF instruction executed).
(6) Timer LC
Timer LC is a 4-bit binary down counter with the timer LC
reload register (RLC). Data can be set simultaneously in timer
LC and the reload register (RLC) with the TLCA instruction.
Timer LC starts counting after the following process;
set data in timer LC,
select the count source with the bit 1 of register W3,
set the bit 0 of register W3 to “1.”
Timer LC is the timer for LCD clock generating. Also, it can
be used as the multi-carrier generator by setting the bit 1 of
register W3 to “1” and selecting the system clock (STCK) as
a count source. When the multi-carrier generator is selected,
the waveform which is the timer LC underflow signal divided
by 2 can be output as a carrier wave from port CARR. At this
time, stop the carrier generating circuit and LCD control circuit.
When the multi-carrier generator (duty ratio: 1/2 fixed) is used,
the enable/stop of the carrier wave output from port CARR
can be set by the stop of timer LC or the carrier wave output
auto-control function by timer 1.
(7) Timer interrupt request flags (T1F and T2F)
Each timer interrupt request flag is set to “1” when each timer
underflows. The state of these flags can be examined with
the skip instructions (SNZT1 and SNZT2).
Use the interrupt control register V1 to select an interrupt or
a skip instruction.
An interrupt request flag is cleared to “0” when an interrupt
occurs or when the next instruction is skipped with a skip
instruction.
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