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參數(shù)資料
| 型號(hào)： | M34551 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER |
| 中文描述： | 單芯片4位CMOS微機(jī)紅外遙控器 |
| 文件頁數(shù)： | 33/68頁 |
| 文件大?。?/td> | 698K |
| 代理商： | M34551 |
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33
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
POWER DOWN FUNCTION
The 4551 Group has 2-type power down functions.
G
Clock operating mode .................................. POF instruction
G
RAM back-up mode.................................... POF2 instruction
Power down is performed by executing each instruction. Above
power down functions are different from reset in start conditions.
Table 15 shows the function and states retained at power down.
Figure 36 shows the state transition.
G
Return from power down state ............. Warm start condition
G
Return from reset state .......................... Cold start condition
(1) Clock operating mode
The following functions and states are retained.
G
RAM
G
Reset circuit
G
X
CIN
–X
COUT
oscillation
G
LCD display
G
Timer 2
(2) RAM back-up mode
The following functions and states are retained.
G
RAM
G
Reset circuit
Unlike the clock operating mode, all oscillations stop in the
RAM back-up mode.
(3) Warm start condition
The system returns from the power down state when;
G
the external wakeup signal is input or the timer 2 underflow
occurs
in the clock operating mode, or when;
G
the external wakeup signal is input
in the RAM back-up mode.
In either case, the CPU starts executing the software from
address 0 in page 0. In this case, the P flag is “1.”
(4) Cold start condition
The CPU starts executing the software from address 0 in
page 0 when;
G
reset pulse is input to
RESET
pin, or
G
reset by watchdog timer is performed.
In this case, the P flag is “0.”
Table 15 Functions and states retained at power down
Power down
Clock
operating
RAM
back-up
O
O
O
O
O
(Note 3)
O
(Note 4)
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Function
Program counter (PC), registers A, B,
carry flag (CY), stack pointer (SP) (Note 2)
Contents of RAM
Port level
Clock control register MR
Timer control register W1
Timer control registers W2, W3
Interrupt control register V1
Interrupt control register I1
Carrier wave control registers and flag (C1, C2, CR)
LCD display function
LCD control registers L1, L2
Timer LC
Timer 1 function
Timer 2 function
External 0 interrupt request flag (EXF0)
Timer 1 interrupt request flag (T1F)
Timer 2 interrupt request flag (T2F)
Watchdog timer flag (WDF)
Watchdog timer enable flag (WEF)
Interrupt enable flag (INTE)
General-purpose register V2
Notes 1: “O” represents that the function can be retained, and
“
” represents that the function is initialized.
Registers and flags other than the above are undefined
at power down, and set an initial value after returning.
2: The stack pointer (SP) points the level of the stack
register and is initialized to “111
2
” at power down.
3: LCD is turned off.
4: The state of the timer is undefined.
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