參數(shù)資料
型號(hào)： M34551
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER
中文描述： 單芯片4位CMOS微機(jī)紅外遙控器
文件頁數(shù)： 13/68頁
文件大小： 698K
代理商： M34551
13
MITSUBISHI MICROCOMPUTERS
4551 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for
INFRARED REMOTE CONTROL TRANSMITTER
INTERRUPT FUNCTION
The interrupt type is a vectored interrupt branching to an individual
address (interrupt address) according to each interrupt source.
An interrupt occurs when the following 3 conditions are satisfied.
Interrupt enable flag (INTE) = “1” (Interrupt enabled)
Interrupt enable bit = “1” (Interrupt request occurrence enabled)
An interrupt activated condition is satisfied
(request flag = “1”)
Table 3 shows interrupt sources. (Refer to each interrupt request
flag for details of activated conditions.)
(1) Interrupt enable flag (INTE)
The interrupt enable flag (INTE) controls whether the every
interrupt enable/disable. Interrupts are enabled when INTE
flag is set to “1” with the EI instruction and disabled when
INTE flag is cleared to “0” with the DI instruction. When any
interrupt occurs, the INTE flag is automatically cleared to “0,”
so that other interrupts are disabled until the EI instruction is
executed.
(2) Interrupt enable bits (V1
0
–V1
3
)
Use an interrupt enable bit of interrupt control register V1 to
select the corresponding interrupt request or skip instruction.
Table 4 shows the interrupt request flag, interrupt enable bit
and skip instruction.
Table 5 shows the interrupt enable bit function.
(3) Interrupt request flag
When the activated condition for each interrupt is satisfied,
the corresponding interrupt request flag is set to “1.” Each
interrupt request flag is cleared to “0” when either;
an interrupt occurs, or
the next instruction is skipped with a skip instruction.
Each interrupt request flag is set when the activated condition
is satisfied even if the interrupt is disabled by the INTE flag or
its interrupt enable bit. Once set, the interrupt request flag
retains set until a clear condition is satisfied.
Accordingly, an interrupt occurs when the interrupt disable
state is released while the interrupt request flag is set.
If more than one interrupt request flag is set when the interrupt
disable state is released, the interrupt priority level is as follows
shown in Table 3.
Table 3 Interrupt sources
Priority
level
1
External 0 interrupt
2
3
Interrupt
address
Address 0
in page 1
Address 4
in page 1
Address 6
in page 1
Interrupt name
Timer 1 interrupt
Timer 2 interrupt
Activated condition
Level change of
INT pin
Timer 1 underflow
Timer 2 underflow
Table 4 Interrupt request flag, interrupt enable bit and skip
instruction
Interrupt name
External 0 interrupt
Timer 1 interrupt
Timer 2 interrupt
T2F
Skip instruction
SNZ0
SNZT1
SNZT2
Request flag
EXF0
T1F
Enable bit
V1
0
V1
2
V1
3
Table 5 Interrupt enable bit function
Skip instruction
Invalid
Valid
Interrupt enable bit
1
0
Occurrence of
interrupt request
Enabled
Disabled
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