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| 型號(hào)： | M34524MC-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64 |
| 文件頁(yè)數(shù)： | 94/163頁(yè) |
| 文件大?。?/td> | 1235K |
| 代理商： | M34524MC-XXXFP |
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Rev.2.00
Jul 27, 2004
page 34 of 159
REJ03B0091-0200Z
4524 Group
Fig. 26 Timer structure (2)
Register A
Reload control circuit
(TAB4)
W43
Q
R
T
(T4AB)
Timer 4 (8)
Register B
Reload register R4H (8)
(TAB4)
(T4AB)
PWMOD
(T4R4L)
T4F
ORCLK
XIN
1
W41
0
Timer 4,
Serial I/O
interrupt
1
W40
0
(T4HAB)
T3UDF
PWMOD
Port C output
Q
C/CNTR1
W31
W30
R
D
T
W32
W61
1
W52
0
Timer 5 (16)
1 - - 4 - - - - - - - -13 14 15 16
W51, W50
01
00
10
11
T5F
Timer 5
interrupt
Timer 5 underflow signal (T5UDF)
XCIN
1
W63
0
1/2
LCD clock
Reload register RLC (4)
Timer LC (4)
Register A
(TLCA)
1
W62
0
ORCLK
Watchdog
reset signal
Watchdog timer (16)
Q
S
Q
T
D
WDF2
Reset signal
R
Q
R
S
WEF
Reset signal
R
WDF1
WRST
instruction
INSTCK
+
DWDT instruction
WRST instruction
1 - - - - - - - - - - - - - - - - - - - 16
INSTCK :
ORCLK :
Instruction clock (system clock divided by 3)
Prescaler output (instruction clock divided by 1 to 256)
(Note 4)
(Note 5)
PWMOUT
(To timer 2 and timer 3)
0
W42
1
“H” interval
expansion
(Note 4)
(Note 6)
(Note 4)
(Note 8)
(Note 7)
1/2
Register A
Register B
Reload register R4L (8)
Data is set automatically from each reload
register when timer underflows
(auto-reload function).
Notes 4: Count source is stopped by clearing to “0.”
5: XIN cannot be used as count source when bit 1 (MR1) of register MR
is set to “1” and f(XIN) oscillation is stopped.
6: This timer is initialized (initial value = FFFF16) by stop of count
source (W52 = “0”).
7: Flag WDF1 is cleared to “0” and the next instruction is skipped when
the WRST instruction is executed while flag WDF1 = “1”.
The next instruction is not skipped even when the WRST instruction
is executed while flag WDF1 = “0”.
8: Flag WEF is cleared to “0” and watchdog timer reset does not occur
when the DWDT instruction and WRST instruction are executed
continuously.
9: The WEF flag is set to “1” at system reset or RAM back-up mode.
1
I30
0
SIOF
(From Serial I/O)
(Note 9)
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