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參數(shù)資料
| 型號： | M34524MC-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64 |
| 文件頁數(shù)： | 127/163頁 |
| 文件大?。?/td> | 1235K |
| 代理商： | M34524MC-XXXFP |
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Rev.2.00
Jul 27, 2004
page 64 of 159
REJ03B0091-0200Z
4524 Group
Program counter (PC) ..........................................................................................................
Address 0 in page 0 is set to program counter.
Interrupt enable flag (INTE) ..................................................................................................
Power down flag (P) .............................................................................................................
External 0 interrupt request flag (EXF0) ..............................................................................
External 1 interrupt request flag (EXF1) ..............................................................................
Interrupt control register V1 ..................................................................................................
Interrupt control register V2 ..................................................................................................
Interrupt control register I1 ...................................................................................................
Interrupt control register I2 ...................................................................................................
Interrupt control register I3 ...................................................................................................
Timer 1 interrupt request flag (T1F) .....................................................................................
Timer 2 interrupt request flag (T2F) .....................................................................................
Timer 3 interrupt request flag (T3F) .....................................................................................
Timer 4 interrupt request flag (T4F) .....................................................................................
Timer 5 interrupt request flag (T5F) .....................................................................................
Watchdog timer flags (WDF1, WDF2) ..................................................................................
Watchdog timer enable flag (WEF) ......................................................................................
Timer control register PA ......................................................................................................
Timer control register W1 .....................................................................................................
Timer control register W2 .....................................................................................................
Timer control register W3 .....................................................................................................
Timer control register W4 .....................................................................................................
Timer control register W5 .....................................................................................................
Timer control register W6 .....................................................................................................
Clock control register MR .....................................................................................................
Serial I/O transmit/receive complation flag (SIOF) ..............................................................
Serial I/O mode register J1 ..................................................................................................
Serial I/O register SI .............................................................................................................
A/D conversion completion flag (ADF) .................................................................................
A/D control register Q1 .........................................................................................................
A/D control register Q2 .........................................................................................................
A/D control register Q3 .........................................................................................................
Successive approximation register AD ................................................................................
Comparator register ..............................................................................................................
LCD control register L1 ........................................................................................................
LCD control register L2 ........................................................................................................
“” represents undefined.
Fig. 50 Internal state at reset
(2) Internal state at reset
Figure 50 and 51 show internal state at reset (they are the same af-
ter system is released from reset). The contents of timers, registers,
flags and RAM except shown in Figure 50 are undefined, so set the
initial value to them.
000
00
0
(Interrupt disabled)
0
(Interrupt disabled)
0
(Interrupt disabled)
0
000
0
000
0
1
0
(Prescaler stopped)
0
(Timer 1 stopped)
0
(Timer 2 stopped)
0
(Timer 3 stopped)
0
(Timer 4 stopped)
0
(Timer 5 stopped)
0
(Timer LC stopped)
1
100
0
(External clock selected,
serial I/O port not selected)
0
000
0
000
0
000
0
000
1
111
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