參數(shù)資料
型號(hào): M34524M8-XXXFP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP64
封裝: 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64
文件頁數(shù): 27/66頁
文件大?。?/td> 1936K
代理商: M34524M8-XXXFP
Rev.1.04
Aug 23, 2007
Page 33 of 146
REJ03B0188-0104
4559 Group
Fig 34. Timers structure (2)
Watchdog reset
signal
reset signal
(Note 2)
D
T
Q
R
DWDT instruction
+
WRST instruction
Reset signal
(Note 3)
(Note 1)
WRST instruction
Watchdog timer (16)
1 - - - - - - - - - - - - - 16
INSTCK
S
R
Q
WDF1
S
R
Q
WEF
Note 1: Flag WDF1 is cleared to “0” and the next instruction is skipped when the WRST instruction is executed
while flag WDF1 = “1”.
The WRST instruction is equivalent to the NOP instruction while flag WDF1 = “0”.
2: Flag WEF is cleared to “0” and watchdog timer reset does not occur when the DWDT instruction and
WRST instruction are executed continuously.
3: The WEF flag is set to “1” at system reset or RAM back-up mode.
Data is set automatically from each reload register
when timer underflows (auto-reload function).
W42
0
1
W43
Timer LC (4)
Reload register RLC (4)
(TLCA)
Register A
Timer 3
interrupt
STCK
T3F
Timer 3 underflow signal
(T3UDF)
LCD
clock
1/2
00
01
10
11
W31, W30
Timer 3 (16)
1 - - 4 - - - - - 13 14 15 16
W33
0
1
W32
XCIN
ORCLK
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