參數(shù)資料
型號(hào)： M34524M8-XXXFP
元件分類(lèi)： 微控制器/微處理器
英文描述： 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP64
封裝： 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64
文件頁(yè)數(shù)： 16/66頁(yè)
文件大?。?/td> 1936K
代理商： M34524M8-XXXFP
Rev.1.04
Aug 23, 2007
Page 23 of 146
REJ03B0188-0104
4559 Group
INTERRUPT FUNCTION
The interrupt type is a vectored interrupt branching to an
individual address (interrupt address) according to each interrupt
source. An interrupt occurs when the following 3 conditions are
satisfied.
An interrupt activated condition is satisfied (request flag =
“1”)
Interrupt enable bit is enabled (“1”)
Interrupt enable flag is enabled (INTE = “1”)
Table 10 shows interrupt sources. (Refer to each interrupt request
flag for details of activated conditions.)
(1) Interrupt enable flag (INTE)
The interrupt enable flag (INTE) controls whether the every
interrupt enable/disable. Interrupts are enabled when INTE flag
is set to “1” with the EI instruction and disabled when INTE flag
is cleared to “0” with the DI instruction. When any interrupt
occurs, the INTE flag is automatically cleared to “0,” so that
other interrupts are disabled until the EI instruction is executed.
(2) Interrupt enable bit
Use an interrupt enable bit of interrupt control registers V1 and
V2 to select the corresponding interrupt or skip instruction.
Table 11 shows the interrupt request flag, interrupt enable bit and
skip instruction.
Table 12 shows the interrupt enable bit function.
(3) Interrupt request flag
When the activated condition for each interrupt is satisfied, the
corresponding interrupt request flag is set to “1.” Each interrupt
request flag except the voltage drop detection circuit interrupt
request flag is cleared to “0” when either;
an interrupt occurs, or
a skip instruction is executed.
The voltage drop detection circuit interrupt request flag cannot
be cleared to “0” at the state that the activated condition is
satisfied.
Each interrupt request flag is set when the activated condition is
satisfied even if the interrupt is disabled by the INTE flag or its
interrupt enable bit. Once set, the interrupt request flag retains set
until a clear condition is satisfied.
Accordingly, an interrupt occurs when the interrupt disable state
is released while the interrupt request flag is set.
If more than one interrupt request flag is set when the interrupt
disable state is released, the interrupt priority level is as follows
shown in Table 10.
Table 10 Interrupt sources
Priority
level
Interrupt source
Interrupt
address
Interrupt name
Activated
condition
1
External 0
interrupt
Level change of
INT0 pin
Address 0
in page 1
2
Timer 1 interrupt
Timer 1
underflow
Address 4
in page 1
3
Timer 2 interrupt
Timer 2
underflow
Address 6
in page 1
4
Timer 3 interrupt
Timer 3
underflow
Address 8
in page 1
Table 11 Interrupt request flag, interrupt enable bit
and skip instruction
Interrupt name
Interrupt
request
flag
Skip
instruction
Interrupt
enable bit
External 0 interrupt EXF0
SNZ0
V10
Timer 1 interrupt
T1F
SNZT1
V12
Timer 2 interrupt
T2F
SNZT2
V13
Timer 3 interrupt
T3F
SNZT3
V20
Table 12 Interrupt enable bit function
Interrupt enable
bit
Occurrence of
interrupt
Skip instruction
1
Enabled
Invalid
0
Disabled
Valid
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M34524MC-XXXFP 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES
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M3452-C125K2,A 制造商:Bonitron 功能描述:OVERVOLTAGE BRAKING TRANSISTOR
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