參數(shù)資料
型號(hào)： M34514M8
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
中文描述： 單芯片4位微機(jī)的CMOS
文件頁(yè)數(shù)： 21/106頁(yè)
文件大?。?/td> 1304K
代理商： M34514M8
21
4513/4514 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
(4) Internal state during an interrupt
The internal state of the microcomputer during an interrupt is as fol-
lows (Figure 14).
Program counter (PC)
An interrupt address is set in program counter. The address to be
executed when returning to the main routine is automatically
stored in the stack register (SK).
Interrupt enable flag (INTE)
INTE flag is cleared to “0” so that interrupts are disabled.
Interrupt request flag
Only the request flag for the current interrupt source is cleared to
“0.”
Data pointer, carry flag, skip flag, registers A and B
The contents of these registers and flags are stored automatically
in the interrupt stack register (SDP).
(5) Interrupt processing
When an interrupt occurs, a program at an interrupt address is ex-
ecuted after branching a data store sequence to stack register.
Write the branch instruction to an interrupt service routine at an in-
terrupt address.
Use the RTI instruction to return from an interrupt service routine.
Interrupt enabled by executing the EI instruction is performed after
executing 1 instruction (just after the next instruction is executed).
Accordingly, when the EI instruction is executed just before the RTI
instruction, interrupts are enabled after returning the main routine.
(Refer to Figure 13)
Fig. 13 Program example of interrupt processing
Program counter (PC)
.............................................................. Each interrupt address
Stack register (SK)
.............................................The address of main routine to be
executed when returning
Interrupt enable flag (INTE)
.................................................................. 0 (Interrupt disabled)
Interrupt request flag (only the flag for the current interrupt
source)................................................................................... 0
Data pointer, carry flag, registers A and B, skip flag
........ Stored in the interrupt stack register (SDP) automatically
Fig. 15 Interrupt system diagram
Fig. 14 Internal state when interrupt occurs
EI
RTI
Interrupt
service routine
Interrupt
occurs
Interrupt is
enabled
Main
rouine
: Interrupt enabled state
: Interrupt disabled state
T1F
V1
2
EXF1
V1
1
EXF0
V1
0
Address 2
in page 1
Address 4
in page 1
Address 0
in page 1
T4F
V2
1
T3F
V2
0
T2F
V1
3
Address 8
in page 1
Address A
in page 1
Address 6
in page 1
SIOF
V2
3
Enable
bit
ADF
V2
2
Completion of
serial I/O transfer
Timer 1
underflow
Timer 4
underflow
Timer 3
underflow
Timer 2
underflow
Completion of
A-D conversion
Address E
in page 1
Address C
in page 1
Request flag
(state retained)
Enable
flag
INTE
Activated
condition
INT0 pin
(L
→
H or
H
→
L input)
INT1 pin
(L
→
H or
H
→
L input)
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