參數(shù)資料
型號(hào): M34509G4FP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDSO24
封裝: 5.30 X 10.10 MM, 0.80 MM PITCH, PLASTIC, SSOP-24
文件頁(yè)數(shù): 95/145頁(yè)
文件大?。?/td> 1060K
代理商: M34509G4FP
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)當(dāng)前第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)
4509 Group
Rev.1.03
2009.07.27
page 51 of 140
REJ03B0147-0103
RAM BACK-UP MODE
The 4509 Group has the RAM back-up mode.
When the POF instruction is executed continuously after the EPOF
instruction, system enters the RAM back-up state.
The POF instruction is equal to the NOP instruction when the EPOF
instruction is not executed before the POF instruction.
As oscillation stops retaining RAM, the function of reset circuit and
states at RAM back-up mode, current dissipation can be reduced
without losing the contents of RAM.
Table 19 shows the function and states retained at RAM back-up.
Figure 46 shows the state transition.
(1) Identification of the start condition
Warm start (return from the RAM back-up state) or cold start (return
from the normal reset state) can be identified by examining the state
of the power down flag (P) with the SNZP instruction.
(2) Warm start condition
When the external wakeup signal is input after the system enters the
RAM back-up state by executing the EPOF instruction and POF in-
struction continuously, the CPU starts executing the program from
address 0 in page 0. In this case, the P flag is “1.”
(3) Cold start condition
The CPU starts executing the program from address 0 in page 0
when;
“L” level is applied to RESET pin,
system reset (SRST) is performed,
reset by watchdog timer is performed,
reset by the built-in power-on reset circuit is performed (only for H
version), or
reset by the voltage drop detection circuit is performed (only for H
version).
In this case, the P flag is “0.”
Table 19 Functions and states retained at RAM back-up
Function
Program counter (PC), registers A, B,
carry flag (CY), stack pointer (SP) (Note 2)
Contents of RAM
Interrupt control registers V1, V2
Interrupt control register I1
Selected oscillation circuit (execution of CRCK)
Clock control register MR
Clock control register RG
Timer 1, Timer 2 function
Watchdog timer function
Timer control register PA
Timer control registers W1, W2
Timer control registers W5, W6
Serial interface function
Serial interface control register J1
A/D conversion function
A/D control register Q1
Voltage drop detection circuit
Port level
Key-on wakeup control registers K0 to K2, L1
Pull-up control registers PU0 to PU2
Port output structure control registers FR0 to FR3, C1
External interrupt request flag (EXF0)
Timer interrupt request flags (T1F, T2F)
A/D conversion completion flag (ADF)
Serial interface transmit/receive completion flag
(SIOF)
Interrupt enable flag (INTE)
Watchdog timer flags (WDF1, WDF2)
Watchdog timer enable flag (WEF)
RAM back-up
O
O
(Note 3)
(Note 4)
O
O
O
(Note 5)
O
(Note 3)
(Note 4)
Notes 1:“O” represents that the function can be retained, and “” represents
that the function is initialized.
Registers and flags other than the above are undefined at RAM
back-up, and set an initial value after returning.
2: The stack pointer (SP) points the level of the stack register and is
initialized to “7” at RAM back-up.
3: The state of the timer is undefined.
4: Initialize the watchdog timer flag WDF1 with the WRST instruction,
and then set the system to be in the RAM back-up mode.
5: The voltage drop detection circuit is equipped with only H version.
In the RAM back-up mode, when the SVDE instruction is not ex-
ecuted, the voltage drop detection circuit is invalid, and when the
SVDE instruction is executed, the voltage drop detection circuit is
valid.
相關(guān)PDF資料
PDF描述
M34509G4HFP 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDSO24
M34509G4-XXXFP 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDSO24
M34509G4H-XXXFP 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDSO24
M34510M4A-XXXSP 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDIP32
M34510M2A-XXXFP 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO36
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M34509G4HFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
M34509G4H-XXXFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
M34509G4-XXXFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
M34509T2-CPE 功能描述:DEV TOOL COMPACT EMULATOR: 4508/ RoHS:否 類別:編程器,開(kāi)發(fā)系統(tǒng) >> 內(nèi)電路編程器、仿真器以及調(diào)試器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 19/Jul/2010 標(biāo)準(zhǔn)包裝:1 系列:* 類型:* 適用于相關(guān)產(chǎn)品:* 所含物品:*
M34512M2 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER