參數(shù)資料
型號(hào): M34509G4FP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDSO24
封裝: 5.30 X 10.10 MM, 0.80 MM PITCH, PLASTIC, SSOP-24
文件頁(yè)數(shù): 117/145頁(yè)
文件大小: 1060K
代理商: M34509G4FP
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)當(dāng)前第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)
4509 Group
Rev.1.03
2009.07.27
page 71 of 140
REJ03B0147-0103
CONTROL REGISTERS
I13
I12
I11
I10
INT pin input control bit (Note 2)
Interrupt valid waveform for INT pin/
return level selection bit (Note 2)
INT pin edge detection circuit control bit
INT pin
timer 1 control enable bit
Interrupt control register I1
R/W
TAI1/TI1A
at RAM back-up : state retained
at reset : 00002
INT pin input disabled
INT pin input enabled
Falling waveform (“L” level of INT pin is recognized with the SNZI0
instruction)/“L” level
Rising waveform (“H” level of INT pin is recognized with the SNZI0
instruction)/“H” level
One-sided edge detected
Both edges detected
Disabled
Enabled
0
1
0
1
0
1
0
1
Interrupt disabled (SNZSI instruction is valid)
Interrupt enabled (SNZSI instruction is invalid)
Interrupt disabled (SNZAD instruction is valid)
Interrupt enabled (SNZAD instruction is invalid)
This bit has no function, but read/write is enabled.
R/W
TAV2/TV2A
V13
V12
V11
V10
V23
V22
V21
V20
Serial interface interrupt enable bit
A/D interrupt enable bit
Not used
Interrupt control register V2
at RAM back-up : 00002
at reset : 00002
0
1
0
1
0
1
0
1
Interrupt control register V1
Timer 2 interrupt enable bit
Timer 1 interrupt enable bit
Not used
External 0 interrupt enable bit
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
0
1
0
1
0
1
0
1
at RAM back-up : 00002
at reset : 00002
R/W
TAV1/TV1A
at RAM back-up : 00002
at reset : 00002
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set.
3: Main clock cannot be stopped when the main clock is selected for the operation source clock.
4: The stopped clock cannot be selected for the operation source clock. In order to switch the operation source clock, generate the oscillation stabiliz-
ing wait time by software first and set the oscillation of the destination clock to be enabled.
5: On-chip oscillator cannot be stopped when the on-chip oscillator is selected for the operation source clock.
MR3
Clock control register MR
Operation mode
Through mode (frequency not divided)
Frequency divided by 2 mode
Frequency divided by 4 mode
Frequency divided by 8 mode
Main clock (f(XIN)) oscillation enabled
Main clock (f(XIN)) oscillation stop
Main clock (f(XIN))
On-chip oscillator clock (f(RING))
at reset : 11012
at RAM back-up : 11012
MR3
0
1
R/W
TAMR/TMRA
Operation mode selection bits
0
1
0
1
MR2
0
1
0
1
MR1
MR0
MR2
0
1
On-chip oscillator (f(RING)) oscillation enabled
On-chip oscillator (f(RING)) oscillation stop
Clock control register RG
W
TRGA
at RAM back-up : 02
at reset : 02
RG0
Main clock f(XIN) control bit (Note 3)
Operation source clock selection bit (Note 4)
On-chip oscillator (f(RING)) control bit
(Note 5)
相關(guān)PDF資料
PDF描述
M34509G4HFP 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDSO24
M34509G4-XXXFP 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDSO24
M34509G4H-XXXFP 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDSO24
M34510M4A-XXXSP 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDIP32
M34510M2A-XXXFP 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO36
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M34509G4HFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
M34509G4H-XXXFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
M34509G4-XXXFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
M34509T2-CPE 功能描述:DEV TOOL COMPACT EMULATOR: 4508/ RoHS:否 類別:編程器,開(kāi)發(fā)系統(tǒng) >> 內(nèi)電路編程器、仿真器以及調(diào)試器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 19/Jul/2010 標(biāo)準(zhǔn)包裝:1 系列:* 類型:* 適用于相關(guān)產(chǎn)品:* 所含物品:*
M34512M2 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER