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參數(shù)資料
| 型號： | M34508G4H-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | 5.30 X12.60 MM, 1.27 MM PITCH, PLASTIC, SOP-20 |
| 文件頁數(shù)： | 70/106頁 |
| 文件大小： | 1059K |
| 代理商： | M34508G4H-XXXFP |
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Rev.1.03
2009.07.27
page 64 of 140
REJ03B0148-0103
4508 Group
Note [2] on bit 3 of register I1
When the bit 3 of register I1 is cleared to “0”, the RAM back-up
mode is selected and the input of INT pin is disabled, be careful
about the following notes.
When the INT pin input is disabled (register I13 = “0”), set the key-
on wakeup of INT pin to be invalid (register L10 = “0”) before
system enters to the RAM back-up mode. (refer to Figure 58).
LA
0
; (02)
TI1A
; INT key-on wakeup disabled ...........
DI
EPOF
POF2
; RAM back-up
: these bits are not used here.
Fig. 58 External 0 interrupt program example-2
Note [3] on bit 2 of register I1
When the interrupt valid waveform of the P13/INT pin is changed
with the bit 2 of register I1 in software, be careful about the fol-
lowing notes.
Depending on the input state of the P13/INT pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 2 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 59)
and then, change the bit 2 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to
“0” after executing at least one instruction (refer to Figure 59).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ0 instruction (refer to Figure 59).
LA
4
; (02)
TV1A
; The SNZ0 instruction is valid ...........
LA
12
; (12)
TI1A
; Interrupt valid waveform is changed
NOP
...........................................................
SNZ0
; The SNZ0 instruction is executed
(EXF0 flag cleared)
NOP
...........................................................
: these bits are not used here.
Fig. 59 A/D conversion interrupt program example
LA
4
; (02)
TV1A
; The SNZ0 instruction is valid ...........
LA
8
; (12)
TI1A
; Control of INT pin input is changed
NOP
...........................................................
SNZ0
; The SNZ0 instruction is executed
(EXF0 flag cleared)
NOP
...........................................................
: these bits are not used here.
Fig. 57 External 0 interrupt program example-1
P13/INT pin
Note [1] on bit 3 of register I1
When the input of the INT pin is controlled with the bit 3 of regis-
ter I1 in software, be careful about the following notes.
Depending on the input state of the P13/INT pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 3 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 57)
and then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to
“0” after executing at least one instruction (refer to Figure 57).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ0 instruction (refer to Figure 57).
10
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