參數(shù)資料
型號: M34280M1-XXXGP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20
封裝: 0.225 INCH, 0.65 MM PITCH, PLASTIC, SSOP-20
文件頁數(shù): 31/48頁
文件大?。?/td> 605K
代理商: M34280M1-XXXGP
Interrupt
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
36
Maskable interrupt :
An interrupt which can be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority can be changed by priority level.
Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.
Figure 1.10.1. Classification of interrupts
Interrupt
Software
Hardware
Special
Peripheral I/O (Note)
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
Reset
_______
NMI
________
DBC
Watchdog timer
Single step
Address matched
Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system.
Overview of Interrupt
Type of Interrupts
Figure 1.10.1 lists the types of interrupts.
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