10
10-199
Ver.0.10
MULTIJUNCTION TIMERS
10.8 TOD (Output-related 16-bit Timer)
10.8.12
Operation in TOD Delayed Single-shot Output Mode (without Correction Function)
(1) Outline of TOD delayed single-shot output mode
In delayed single-shot output mode, the timer generates a pulse in width of (reload 0 register set
value + 1) only once, with the output delayed by an amount of time equal to (counter set value +
1) and then stops without performing any operation.
When after setting the counter and reload 0 register, the timer is enabled (by writing to the enable
bit in software or by TID1 underflow/overflow signal), it starts counting down from the counter's
set value synchronously with the count clock. The first time the counter underflows, the reload 0
register value is loaded into the counter causing it to continue counting down, and the counter
stops when it underflows next time.
The F/F output waveform in delayed single-shot output mode is inverted (F/F output levels
change from low to high, or vice versa) when the counter underflows first time and next,
generating a single-shot pulse waveform in width of (reload 0 register set value + 1) only once,
with the output delayed by an amount of time equal to (first set value of counter + 1). Also, an
interrupt can be generated when the counter underflows first time and next.
The valid count values are the (counter set value + 1) and (reload 0 register set value + 1). For
details about count operation, also see Section 10.3.12, "Operation in TOP Delayed Single-shot
Output Mode (With Correction Function)."
(2) Precautions to be observed when using TOD delayed single-shot output mode
The following describes precautions to be observed when using TOD delayed single-shot output
mode.
If the counter stops due to underflow in the same clock period as the timer is enabled by
external input, the former has priority (so that the counter stops).
If the counter stops due to underflow in the same clock period as count is enabled by writing to
the enable bit, the latter has priority (so that count is enabled).
If the timer is enabled by external input in the same clock period as count is disabled by writing
to the enable bit, the latter has priority (so that count is disabled).
When you read the counter immediately after reloading it pursuant to underflow, the value you
get is temporarily H'FFFF. But this counter value immediately changes to (reload value - 1) at
the next clock edge.
Because the internal circuit operation is synchronized to the prescaler output, a finite time
equal to a prescaler delay is included before F/F starts operating after the timer is enabled.