9
9-2
Ver.0.10
9.1 Outline of the DMAC
The 32170 contains a 10 channel-DMA (Direct Memory Access) Controller. It allows you to transfer
data at high speed between internal peripheral I/Os, between internal RAM and internal peripheral I/O,
and between internal RAMs, as requested by a software trigger or from an internal peripheral I/O.
Table 9.1.1 Outline of the DMAC
Item
Description
Number of channel
10 channels
Transfer request
Software trigger
Request from internal peripheral I/Os: A-D converter, multijunction timer, or serial
I/O (reception completed, transmit buffer empty)
Transfer operation can be cascaded between DMA channels (Note)
Maximum number
of times transferred
256 times
Transferable
address space
64 Kbytes (address space from H'0080 0000 to H'0080 FFFF)
Transfers between internal peripheral I/Os, between internal RAM and internal
peripheral I/O, between internal RAMs are supported
Transfer data size
16 or 8 bits
Transfer method
Single transfer DMA (control of the internal bus is relinquished for each transfer
performed), dual-address transfer
Transfer mode
Single transfer mode
Direction of transfer
One of three modes can be selected for the source and destination:
Address fixed
Address incremental
Ring buffered
Channel priority
Channel 0 > channel 1 > channel 2 > channel 3 > channel 4 > channel 5 > channel
6 > channel 7 > channel 8 > channel 9 (Priority is fixed)
Maximum transfer rate 13.3 Mbytes per second (with 20 MHz internal peripheral clock)
Interrupt request
Group interrupt request can be generated when each transfer count register underflows.
Transfer area
64 Kbytes from H'0080 0000 to H'0080 FFFF
(Transferable in the entire internal RAM/SFR area)
Note:
Transfer operation can be cascaded between DMA channels as shown below.
Completion of one transfer in channel 0 starts DMA transfer in channel 1
Completion of one transfer in channel 1 starts DMA transfer in channel 2
Completion of one transfer in channel 2 starts DMA transfer in channel 0
Completion of one transfer in channel 3 starts DMA transfer in channel 4
Completion of one transfer in channel 5 starts DMA transfer in channel 6
Completion of one transfer in channel 6 starts DMA transfer in channel 7
Completion of one transfer in channel 7 starts DMA transfer in channel 5
Completion of one transfer in channel 8 starts DMA transfer in channel 9
Completion of all DMA transfers in channel 0 (transfer count register underflow) starts DMA transfer
in channel 5
DMAC
9.1 Outline of the DMAC