參數(shù)資料
型號: M30LW128D110ZA1T
廠商: 意法半導體
英文描述: 128 Mbit (two 64Mbit, x8/x16, Uniform Block, Flash Memories) 3V Supply, Multiple Memory Product
中文描述: 128兆位(兩個64兆比特,x8/x16,統(tǒng)一座,快閃記憶體)3V電源,多記憶體產(chǎn)品
文件頁數(shù): 17/57頁
文件大?。?/td> 860K
代理商: M30LW128D110ZA1T
17/57
M30LW128D
COMMAND INTERFACE
All Bus Write operations to the device are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. As the device contains two internal memo-
ries care must be taken to issue the commands to
the correct address. Commands issued with A23
High will be addressed to the Upper Memory, com-
mands issued with A23 Low will be addressed to
the Lower Memory.
The Commands are summarized in Table 5, Com-
mands. Refer to Table 5 in conjunction with the
text descriptions below.
After power-up or a Reset operation the device en-
ters Read mode.
Read Memory Array Command.
The Read Mem-
ory Array command is used to return the device to
Read mode. One Bus Write cycle is required to is-
sue the Read Memory Array command and return
the device to Read mode. Once the command is
issued the device remains in Read mode until an-
other command is issued. From Read mode Bus
Read operations will access the memory arrays.
After power-up or a reset the device defaults to
Read Array mode (Page Read).
While the Program/Erase Controller is executing a
Program, Erase, Block Protect, Blocks Unprotect
or Protection Register Program operation the de-
vice will not accept the Read Memory Array com-
mand until the operation completes.
Read Electronic Signature Command.
The Read
Electronic Signature command is used to read the
Manufacturer Code, the Device Code, the Block
Protection Status and the Protection Register.
One Bus Write cycle is required to issue the Read
Electronic Signature command. Once the com-
mand is issued subsequent Bus Read operations
read the Manufacturer Code, the Device Code, the
Block Protection Status or the Protection Register
until another command is issued. Refer to Table 7,
Read Electronic Signature, Tables 8 and 9, Word
and Byte-wide Read Protection Register and Fig-
ure 8, Protection Register Memory Map for infor-
mation on the addresses.
Read Query Command.
The Read Query Com-
mand is used to read data from the Common Flash
Interface (CFI) Memory Area. One Bus Write cycle
is required to issue the Read Query Command.
Once the command is issued subsequent Bus
Read operations read from the Common Flash In-
terface Memory Area. See Appendix B, Tables 26,
27, 28, 29, 30 and 31 for details on the information
contained in the Common Flash Interface (CFI)
memory area.
Read Status Register Command.
The Read Sta-
tus Register command is used to read the Status
Register. One Bus Write cycle is required to issue
the Read Status Register command. As the device
contains two Status Registers (one for each inter-
nal memory) the command must be issued to the
same address as the previous operation (Block
Erase, Write to Buffer, Word Program etc.). Once
the command is issued subsequent Bus Read op-
erations to the same internal memory (A23 Low or
A23 High depending on where the command was
issued to) read the Status Register until another
command is issued. If the Bus Read operation is
issued to the other internal memory, then the other
Status Register will be read, giving the status of
the last command issued in the other internal
memory.
The Status Register information is present on the
output data bus (DQ1-DQ7) when the device is en-
abled and Output Enable is Low, V
IL
.
See the section on the Status Register and Table
11 for details on the definitions of the Status Reg-
ister bits
Clear Status Register Command.
The Clear Sta-
tus Register command can be used to reset bits 1,
3, 4 and 5 in the Status Register to ‘0’. One Bus
Write is required to issue the Clear Status Register
command. The command must be issued to the
same address as the previous operation (Block
Erase, Write to Buffer, Word Program etc.).
The bits in the Status Register are sticky and do
not automatically return to ‘0’ when a new Write to
Buffer and Program, Erase, Block Protect, Block
Unprotect or Protection Register Program com-
mand is issued. If any error occurs then it is essen-
tial to clear any error bits in the Status Register by
issuing the Clear Status Register command before
attempting a new Program, Erase or Resume
command.
Block Erase Command.
The Block Erase com-
mand can be used to erase a block. It sets all of
the bits in the block to ‘1’. All previous data in the
block is lost. If the block is protected then the
Erase operation will abort, the data in the block will
not be changed and the Status Register will output
the error.
Two Bus Write operations are required to issue the
command; the second Bus Write cycle latches the
block address in the internal state machine and
starts the Program/Erase Controller. Once the
command is issued subsequent Bus Read opera-
tions read the Status Register. See the section on
the Status Register for details on the definitions of
the Status Register bits.
During Erase, the device being erased will only ac-
cept the Read Status Register and Program/Erase
Suspend commands, ignoring all other com-
mands. The device not being erased will accept
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