參數(shù)資料
型號(hào): M30840MCT-XXXGP
元件分類(lèi): 微控制器/微處理器
英文描述: 32-BIT, MROM, 32 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁(yè)數(shù): 65/89頁(yè)
文件大?。?/td> 764K
代理商: M30840MCT-XXXGP
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5. Electrical Characteristics (M32C/84)
)
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Figure 5.7 VCC1=VCC2=3.3V Timing Diagram (1)
BCLK
RD
18ns.max
-3ns.min
Hi-Z
DB
0ns.min
td(BCLK-RD)
30ns.min(1)
tac1(RD-DB)(2)
CSi
td(BCLK-CS)
18ns.max(1)
ADi
18ns.max(1)
th(BCLK-AD)
0ns.min
th(BCLK-CS)
0ns.min
BHE
tcyc
td(BCLK-AD)
tac1(AD-DB)(2)
WR,WRL,
WRH
18ns.max
0ns.min
BCLK
CSi
18ns.max
ADi
18ns.max
0ns.min
tcyc
BHE
DBi
td(BCLK-WR)
th(BCLK-RD)
th(RD-DB)
th(RD-AD)
tsu(DB-BCLK)
th(RD-CS)
0ns.min
th(BCLK-WR)
td(BCLK-CS)
td(BCLK-AD)
th(BCLK-AD)
th(BCLK-CS)
th(WR-CS)(3)
td(DB-WR)(3)
th(WR-DB)(3)
th(WR-AD)(3)
[Read Timing] (1
φ + 1φ Bus Cycles)
[Write Timing] (1
φ + 1φ Bus Cycles)
Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space)
tw(WR)(3)
Vcc1=Vcc2=3.3V
NOTES:
1. Values guaranteed only when the microcomputer is used independently.
A maximum of 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK).
2. Varies with operation frequency.
tac1(RD-DB)=(tcyc/2 x m-35)ns.max (if external bus cycle is a
φ + bφ, m=(b x 2) + 1)
tac1(AD-DB)=(tcyc x n-35)ns.max (if external bus cycle is a
φ + bφ, n = a + b)
td(DB-WR)=(tcyc x m-20)ns.min
(if external bus cycle is a
φ + bφ, m=b)
th(WR-DB)=(tcyc/2-20)ns.min
th(WR-AD)=(tcyc/2-10)ns.min
th(WR-CS)=(tcyc/2-10)ns.min
tw(WR)=(tcyc/2 x n-15)ns.min
(if external bus cycle is a
φ + bφ, n=(bx2)-1)
NOTES:
3. Varies with operation frequency.
Measurement Conditions
VCC1=VCC2=3.0 to 3.6V
Input high and low voltage: VIH=1.5V, VIL=0.5V
Output high and low voltage: VOH=1.5V, VOL=1.5V
tcyc=
10
f(BCLK)
9
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