參數資料
型號: M30840MCT-XXXGP
元件分類: 微控制器/微處理器
英文描述: 32-BIT, MROM, 32 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數: 54/89頁
文件大?。?/td> 764K
代理商: M30840MCT-XXXGP
Page 58
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5. Electrical Characteristics (M32C/84)
)
T
4
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C
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3
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Figure 5.4 VCC1=VCC2=5V Timing Diagram (2)
BCLK
CSi
ADi
RD
-5ns.min
BHE
ADi
/DBi
26ns.min
td(BCLK-RD)
tsu(DB-BCLK)
tac2(RD-DB)
tdz(RD-AD)
8ns.max
ALE
td(BCLK-ALE)
18ns.max
td(BCLK-CS)
td(AD-ALE)
th(ALE-AD)
th(BCLK-RD)
th(RD-AD)
th(RD-DB)
td(BCLK-AD)
th(BCLK-CS)
th(RD-CS)
th(BCLK-ALE)
tcyc
Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space with the multiplexed bus)
-5ns.min
BCLK
CSi
ADi
BHE
ADi
/DBi
WR,WRL,
WRH
th(WR-CS)
ALE
th(BCLK-WR)
td(DB-WR)
18ns.max
tac2(AD-DB)
[ Read Timing ] (2
φ +2φ Bus Cycle)
Address
(1)
td(AD-ALE)=(tcyc/2 x n-20)ns.min (if external bus cycle is a
φ + bφ, n=a)
th(ALE-AD)=(tcyc/2 x n-10)ns.min (if external bus cycle is a
φ + bφ, n=a)
th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min
tac2(RD-DB)=(tcyc/2 x m-35)ns.max (if external bus cycle is a
φ + bφ, m=(b x 2)-1)
tac2(AD-DB)=(tcyc/2 x p-35)ns.max (if external bus cycle is a
φ + bφ, p={(a+b-1) x 2}+1)
NOTES:
1. Varies with operation frequency:
Data input
Address
(1)
[ Write Timing ] (2
φ +2φ Bus Cycle)
Address
Data output
Address
(2)
td(AD-ALE)=(tcyc/2 x n - 20)ns.min
(if external bus cycle is a
φ + bφ, n=a)
th(ALE-AD)=(tcyc/2 x n -10)ns.min
(if external bus cycle is a
φ + bφ, n=a)
th(WR-AD)=(tcyc/2-10)ns.min,
th(WR-CS)=(tcyc/2-10)ns.min, th(WR-DB)=(tcyc/2-10)ns.min
td(DB-WR)=(tcyc/2 x m-25)ns.min
(if external bus cycle is a
φ + bφ, m=(b x 2)-1)
NOTES:
2. Varies with operation frequency:
Measurement Conditions:
VCC1=VCC2=4.2 to 5.5V
Input high and low voltage:
VIH=2.5V, VIL=0.8V
Output high and low voltage:
VOH=2.0V, VOL=0.8V
Vcc1=Vcc2=5V
-3ns.min
(1)
th(BCLK-AD)
-3ns.min
0ns.min
(1)
18ns.max
-2ns.min
18ns.max
th(WR-DB)
(2)
th(BCLK-AD)
-3ns.min
th(WR-AD)
18ns.max
td(BCLK-WR)
18ns.max
td(BCLK-AD)
td(AD-ALE)
(2)
td(BCLK-CS)
18ns.max
td(BCLK-ALE)
-2ns.min
th(BCLK-ALE)
tcyc
(2)
th(BCLK-CS)
-3ns.min
th(ALE-AD)
(2)
tcyc=
10
f(BCLK)
9
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