deveopmen
Interrupts
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (100-pin version) group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
72
Precautions for Interrupts
(1) Reading addresses 000000
16
and 000002
16
When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and
interrupt request level) in the interrupt sequence from address 000000
16
. When high-speed interrupt
is occurred, CPU read from address 000002
16
.
The interrupt request bit of the certain interrupt will then be set to “0”.
However, reading addresses 000000
16
and 000002
16
by software does not set request bit to “0”.
(2) Setting the stack pointer
The value of the stack pointer immediately after reset is initialized to 000000
16
. Accepting an interrupt
before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in
the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack point
at the beginning of a program. Any interrupt including the NMI interrupt is generated immediately after
executing the first instruction after reset. Set an even number to the stack pointer. When an even
number is set, execution efficiency is increased.
Set an even address to the stack pointer so that operating efficiency is increased.
(3) The NMI interrupt
As for the NMI interrupt pin, an interrupt cannot be disabled. Connect it to the Vcc pin via a resistance
(pull-up) if unused. Be sure to work on it.
The NMI pin also serves as P8
5
, which is exclusively input. Reading the contents of the P8 register
allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time
when the NMI interrupt is input.
Signal of "L" level width more than 1 clock of CPU operation clock (BCLK) is necessary for NMI pin.
(4) External interrupt
Edge sense
Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT
0
to INT
5
regardless of the CPU operation clock.
Level sense
Either an “L” level or an “H” level of 1 cycle of BCLK + at least 200 ns width is necessary for the signal
input to pins INT
0
to INT
5
regardless of the CPU operation clock. (When X
IN
=20MHz and no division
mode, at least 250 ns width is necessary.)
When the polarity of the INT
0
to INT
5
pins is changed, the interrupt request bit is sometimes set to "1".
After changing the polarity, set the interrupt request bit to "0". Figure 1.9.12 shows the procedure for
changing the INT interrupt generate factor.
(5) Rewrite the interrupt control register
When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been gener-
ated. This will depend on the instruction. If this creates problems, use the below instructions to change
the register.
Instructions : AND, OR, BCLR, BSET