deveopmen
Clock synchronous serial I/O mode
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (100-pin version) group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
133
(1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables 1.17.1
and 1.17.2 list the specifications of the clock synchronous serial I/O mode. Figure 1.17.1 shows the
UARTi transmit/receive mode register.
Table 1.17.1. Specifications of clock synchronous serial I/O mode (1)
Item
Transfer data format
Transfer data length: 8 bits
Transfer clock
When internal clock is selected (bit 3 at addresses 0360
16
, 0368
16
, 0338
16
,
0328
16
, 02F8
16
= “0”) : fi/ 2(n+1)
(Note 1) fi = f1, f8, f32
_
CLK is selected by the corresponding port function select register, periph-
eral function select register and peripheral subfunction select register.
When external clock is selected (bit 3 at addresses 0360
16
, 0368
16
, 0338
16
,
0328
16
, 02F8
16
= “1”) : Input from CLKi pin
_
Transmission/reception control
CTS function/RTS function/CTS, RTS function chosen to be invalid
Transmission start condition
To start transmission, the following requirements must be met:
_
Transmit enable bit (bit 0 at addresses 0365
16
, 036D
16
, 033D
16
, 032D
16
, 02FD
16
) = “1”
_
Transmit buffer empty flag (bit 1 at addresses 0365
16
, 036D
16
, 033D
16
, 032D
16
, 02FD
16
) = “0”
_
When CTS function selected, CTS input level = “L”
_
CLK selected by the corresponding port function select register, peripheral
function select register and peripheral subfunction select register.
Furthermore, if external clock is selected, the following requirements must
also be met:
_
CLKi polarity select bit (bit 6 at addresses 0364
16
, 036C
16
, 033C
16
,
032C
16
, 02FC
16
) = “0”: CLKi input level = “H”
_
CLKi polarity select bit (bit 6 at addresses 0364
16
, 036C
16
, 033C
16
,
032C
16
, 02FC
16
) = “1”: CLKi input level = “L”
Reception start condition
To start reception, the following requirements must be met:
_
Receive enable bit (bit 2 at addresses 0365
16
, 036D
16
, 033D
16
, 032D
16
, 02FD
16
) = “1”
_
Transmit enable bit (bit 0 at addresses 0365
16
, 036D
16
, 033D
16
, 032D
16
, 02FD
16
) = “1”
_
Transmit buffer empty flag (bit 1 at addresses 0365
16
, 036D
16
, 033D
16
, 032D
16
, 02FD
16
) = “0”
Furthermore, if external clock is selected, the following requirements must
also be met:
_
CLKi polarity select bit (bit 6 at addresses 0364
16
, 036C
16
, 033C
16
,
032C
16
, 02FC
16
) = “0”: CLKi input level = “H”
_
CLKi polarity select bit (bit 6 at addresses 0364
16
, 036C
16
, 033C
16
,
032C
16
, 02FC
16
) = “1”: CLKi input level = “L”
When transmitting
_
Transmit interrupt cause select bit (bits 0, 1 at address 0370
16
, bit 4 at address
033D
16
, 032D
16
, 02FD
16
) = “0”: Interrupts requested when data transfer from
UARTi transfer buffer register to UARTi transmit register is completed
_
Transmit interrupt cause select bit (bits 0, 1 at address 0370
16
, bit 4 at
address 033D
16
, 032D
16
, 02FD
16
) = “1”: Interrupts requested when data
transmission from UARTi transfer register is completed
When receiving
_
Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
Note 1: “n” denotes the value 00
16
to FF
16
that is set to the UART bit rate generator.
Note 2: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit is not set to “1”.
Specification
Interrupt request
generation timing