deveopmen
Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (100-pin version) group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
291
Status Register (SRD)
The status register indicates operating status of the flash memory and status such as whether an erase
operation or a program ended successfully or in error. It can be read by writing the read status register
command (70
16
). Also, the status register is cleared by writing the clear status register command (50
16
).
Table 1.32.2 gives the definition of each status register bit. After clearing the reset, the status register
outputs “80
16
”.
Table 1.32.2. Status register (SRD)
Write State Machine (WSM) Status (SR7)
The write state machine (WSM) status indicates the operating status of the flash memory. When
power is turned on, “1” (ready) is set for it. The bit is set to “0” (busy) during an auto write or auto erase
operation, but it is set back to “1” when the operation ends.
Erase Status (SR5)
The erase status reports the operating status of the auto erase operation. If an erase error occurs, it is
set to “1”. When the erase status is cleared, it is set to “0”.
Program Status (SR4)
The program status reports the operating status of the auto write operation. If a write error occurs, it is
set to “1”. When the program status is cleared, it is set to “0”.
Program Status After Program (SR3)
If excessive data is written (phenomenon whereby the memory cell becomes depressed which results
in data not being read correctly), “1” is set for the program status after-program at the end of the page
write operation. In other words, when writing ends successfully, “80
16
” is output; when writing fails,
“90
16
” is output; and when excessive data is written, “88
16
” is output.
If “1” is written for any of the SR5, SR4 or SR3 bits, the page program, block erase, erase all unlocked
blocks and lock bit program commands are not accepted. Before executing these commands, execute
the clear status register command (50
16
) and clear the status register.
SRD0 bits
SR7 (bit7)
SR6 (bit6)
SR5 (bit5)
SR4 (bit4)
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
Status name
Write state machine (WSM) status
Reserved
Erase status
Program status
Block status after program
Reserved
Reserved
Reserved
Definition
"1" "0"
Ready
-
Terminated in error
Terminated in error
Terminated in error
-
-
-
Busy
-
Terminated normally
Terminated normally
Terminated normally
-
-
-