deveopmen
Serial I/O
Preliminary Specifications REV.D
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (100-pin version) group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
121
Figure 1.16.1. Block diagram of UARTi (i = 0 to 2)
n0 : Values set to UART0 bit rate generator (BRG0)
n1 : Values set to UART1 bit rate generator (BRG1)
n2 : Values set to UART2 bit rate generator (BRG2)
RxD2
Reception
control circuit
Transmission
control circuit
1 / (n2+1)
1/16
1/16
1/2
Bit rate
generator
Clock synchronous type
(when internal clock is selected)
UART reception
Clock synchronous type
UART transmission
Clock synchronous type
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is
selected)
Receive
clock
Transmit
clock
CLK2
CTS2 / RTS2
f
1
f
8
f
32
Vcc
RTS
2
CTS
2
TxD2
(UART2)
RxD polarity
reversing circuit
TxD
polarity
reversing
circuit
RxD0
1 / (n0+
1)
1/2
Clock synchronous type
(when internal clock is selected)
UART reception
Clock synchronous type
UART transmission
Clock synchronous type
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is
selected)
Receive
clock
Transmit
clock
CLK0
Clock source selection
f
1
f
8
f
32
CTS0 / RTS0
Reception
control circuit
Transmission
control circuit
Internal
External
Vcc
RTS
0
CTS
0
TxD0
Transmit/
receive
unit
RxD1
1 / (n1+1)
1/16
1/16
1/2
Clock synchronous type
(when internal clock is selected)
UART reception
Clock synchronous type
UART transmission
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is
selected)
Receive
clock
Transmit
clock
CLK1
Clock source selection
f
1
f
8
f
32
Reception
control circuit
Transmission
control circuit
Internal
External
RTS
1
CTS
1
TxD1
(UART1)
(UART0)
CLK
polarity
reversing
circuit
CLK
polarity
reversing
circuit
CTS/RTS disabled
CTS/RTS separated
Clock output pin
select switch
CTS1 / RTS1
/ CTS0 / CLKS1
CTS/RTS disabled
CTS0 from UART1
CTS/RTS selected
CTS/RTS disabled
V
CC
CTS0 to UART0
CTS
0
CTS/RTS disabled
CTS/RTS separated
CTS/RTS disabled
CTS/RTS disabled
CTS/RTS
selected
CLK
polarity
reversing
circuit
Internal
External
Clock source selection
Transmit/
receive
unit
Transmit/
receive
unit
1/16
1/16
Bit rate
generator
Bit rate
generator