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參數(shù)資料
| 型號： | M306K9FCLRP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | 16 X 16 MM, 0.40 MM PITCH, PLASTIC, TQFP-144 |
| 文件頁數(shù)： | 102/294頁 |
| 文件大?。?/td> | 2600K |
| 代理商： | M306K9FCLRP |
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MULTI-MASTER I2C-BUS Interface
Rev.1.00
Jun 06, 2003
page 188 of 290
M16C/6K9 Group
Bit 4: I2C-BUS interface interrupt request bit (PIN)
This bit generates an interrupt request signal. After each byte data is transmitted, the PIN bit changes from
“1” to “0”. At the same time, an I2C interrupt request signal occurs to the CPU. The PIN bit is set to “0”
synchronized with the falling edge of the last internal transmitting clock (including the ACK clock) and an
interrupt request signal occurs synchronized with the falling edge of the PIN bit. When the PIN bit is “0”, the
SCL is kept in the “0” state and clock generation is disabled. In the ACK clock enable mode, if WIT bit (bit 1
of I2C control register 1) is set to “1”, synchronized with the falling edge of last bit clock and ACK clock, PIN
bit becomes to “0” and I2C interrupt request is generated (Refer to the description on bit 1 of I2C control
register 1: the data reception completion interrupt enable bit). Fig.GC-9 shows the timing of I2C interrupt
request generation. The bit is read-only, the value should be “0” in writing.
The PIN bit is set to “0” in one of the following condition:
Executing a write instruction to the I2C data shift register (address 032016, 033016, 031016).
Executing a write instruction to the I2C clock control register (Address : 032416, 033416, 031416)
(only when WIT is “1” and internal WAIT flag is “1”)
When the ES0 bit is “0”
At reset
The PIN bit is set to “0” in one of the following condition:
Immediately after the completion of 1-byte data transmission (including arbitration lost is detected)
Immediately after the completion of 1-byte data reception
In the slave reception mode, with ALS = “0” and immediately after the completion of slave address agreement
or general call address reception
In the slave reception mode, with ALS = “1” and immediately after the completion of address data reception
Bit 5: Bus busy flag (BB)
This bit indicates the in-use status the bus system. When this bit is set to “0”, bus system is not busy and a
START condition can be generated. The BB flag is set/reset by the SCL, SDA pins input signal regardless of
master/slave. This flag is set to “1” by detecting the start condition, and is set to “0” by detecting the stop
condition. The condition of the detecting is set by the start/stop condition setting bits (SSC4–SSC0) of the
I2C start/stop condition control register (address 032516, 033516, 031516). When the ES0 bit (bit 3) of the I2C
control register (address 032316, 033316, 031316) is “0” or reset, the BB flag is set to “0”. For the writing
function to the BB flag, refer to the sections “START Condition Generating Method” and “STOP Condition
Generating Method” described later.
Bit 6: Communication mode specification bit (transfer direction specification bit: TRX)
This bit decides a direction of transfer for data communication. When this bit is “0”, the reception mode is
selected and the data from a transmitting device is received. When the bit is “1”, the transmission mode is
selected and address data and control data are output onto the SDA synchronized with the clock gener-
ated on the SCL. This bit can be set/reset by software or hardware. This bit is set to “1” by hardware in the
following condition:
In slave mode with ALS = “0”, if the AAS flag is set to “1” after the address data reception and the received
___
R/W bit is “1”.
This bit is set to “0” by hardware in one of the following conditions:
When arbitration lost is detected.
When a STOP condition is detected.
When a start condition is prevented by the start condition duplication preventing function (Note).
When a start condition is detected with MST = “0”.
When ACK non-return is detected with MST = “0”.
When ES0 = “0”.
At reset
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