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Preliminary Specifications REV.E
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30220 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory
8
Operation of Functional Blocks
The M30220 group accommodates certain units in a single chip. These units include ROM and RAM to
store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations.
Also included are peripheral units such as timers, real time port, serial I/O, LCD drive control circuit, D-A
converter, A-D converter, DMAC and I/O ports.
The following explains each unit.
Memory
Figure 1.4.1 is a memory map of the M30220 group. The address space extends the 1M bytes from ad-
dress 00000
16
to FFFFF
16
. From FFFFF
16
down is ROM. For example, in the M30220MA-XXXGP, there
is 96K bytes of internal ROM from E8000
16
to FFFFF
16
. The vector table for fixed interrupts such as the
reset and NMI are mapped to FFFDC
16
to FFFFF
16
. The starting address of the interrupt routine is stored
here. The address of the vector table for timer interrupts, etc., can be set as desired using the internal
register (INTB). See the section on interrupts for details.
From 00400
16
up is RAM. For example, in the M30220MA-XXXGP, 6K bytes of internal RAM is mapped to
the space from 00400
16
to 01BFF
16
. In addition to storing data, the RAM also stores the stack used when
calling subroutines and when interrupts are generated.
The SFR area is mapped to 00000
16
to 003FF
16
. This area accommodates the control registers for periph-
eral devices such as I/O ports, A-D converter, serial I/O, timers, and LCD, etc. Figures 1.7.1 to 1.7.3 are
location of peripheral unit control registers. Any part of the SFR area that is not occupied is reserved and
cannot be used for other purposes.
The special page vector table is mapped to FFE00
16
to FFFDB
16
. If the starting addresses of subroutines
or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions
can be used as 2-byte instructions, reducing the number of program steps.
Figure 1.4.1. Memory map
SFR area
For details, see
Figures 1.7.1 to 1.7.3
Internal RAM area
Internal RAM area
Internal ROM area
Reset
Watchdog timer
DBC
NMI
Single step
Address match
BRK instruction
Overflow
Undefined instruction
Special page
vector table
00000
16
00400
16
XXXXX
16
YYYYY
16
FFFFF
16
FFFFF
16
FFFDC
16
FFE00
16
Type No.
Address XXXXX
16
01BFF
16
M30220MA
E8000
16
Address YYYYY
16