Unde
deeopmen
Preliminary Specifications REV.E
Specifications in this manual are tentative and subject to change.
UART2 Special Mode Register
Mitsubishi microcomputers
M30220 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
116
Figure 1.15.26 shows the functional block diagram for I
2
C mode. Setting “1” in the I
2
C mode selection bit
(IICM) causes ports P7
0
, P7
1
, and P7
2
to work as data transmission-reception terminal SDA, clock input-
output terminal SCL, and port P7
2
respectively. A delay circuit is added to the SDA transmission output,
so the SDA output changes after SCL fully goes to “L”. An attempt to read Port P7
1
(SCL) results in
getting the terminal’s level regardless of the content of the port direction register. The initial value of SDA
transmission output in this mode goes to the value set in port P7
0
. The interrupt factors of the bus collision
detection interrupt, UART2 transmission interrupt, and of UART2 reception interrupt turn to the start/stop
condition detection interrupt, acknowledgment non-detection interrupt, and acknowledgment detection
interrupt respectively.
The start condition detection interrupt refers to the interrupt that occurs when the falling edge of the SDA
terminal (P7
0
) is detected with the SCL terminal (P7
1
) staying “H”. The stop condition detection interrupt
refers to the interrupt that occurs when the rising edge of the SDA terminal (P7
0
) is detected with the SCL
terminal (P7
1
) staying “H”. The bus busy flag (bit 2 of the UART2 special mode register) is set to “1” by the
start condition detection, and set to “0” by the stop condition detection.
In the first place, the control bits related to the I
2
C bus (simplified I
2
C bus) interface are explained.
Bit 0 of the UART special mode register (0377
16
) is used as the I
2
C mode selection bit.
Setting “1” in the I
2
C mode select bit (bit 0) goes the circuit to achieve the I
2
C bus (simplified I
2
C bus)
interface effective.
Table 1.15.9 shows the relation between the I
2
C mode select bit and respective control workings.
Since this function uses clock-synchronous serial I/O mode, set this bit to “0” in UART mode.
P7
0
through P7
2
conforming to the simplified I C bus
Selector
I/O
Timer
delay
Noize
Filter
Timer
UART2
Selector
(Port P7
1
output data latch)
I/O
P7
0
/TxD
2
/SDA
P7
1
/RxD
2
/SCL
Reception register
UART2
CLK
Internal clock
UART2
IICM=1
External clock
Selector
UART2
I/O
Timer
P7
2
/CLK
2
Arbitration
IICM=1
Start condition detection
Stop condition detection
Data bus
Falling edge
detection
D
T
Q
D
T
Q
D
T
Q
NACK
ACK
UART2
UART2
R
UART2 transmission/
NACK interrupt
request
UART2 reception/ACK
interrupt request
DMA1 request
9th pulse
IICM=1
IICM=0
IICM=0
IICM=1
IICM=0
IICM=0
IICM=1
IICM=0
IICM=1
IICM=0
Port reading
*
With IICM set to 1, the port terminal is to be readable
even if 1 is assigned to P7
1
of the direction register.
L-synchronous
output enabling bit
S
RQ
Bus busy
IICM=1
IICM=0
Bus collision/start, stop
condition detection
interrupt request
Bus collision
detection
Noize
Transmission
register
To DMA0, DMA1
Q
Noize
To DMA0
Figure 1.15.26. Functional block diagram for I
2
C mode