377
Power Control
M
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t
s
u
M
S
b
i
s
3
M
h
0
I
C
i
m
2
R
i
1
O
c
r
8
C
o
c
o
G
M
m
p
r
P
u
t
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T
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r
p
R
s
o
U
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I
N
G
L
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-
C
H
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P
1
6
-
B
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M
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2.14.2 Stop Mode Set-Up
(1) Enables the interrupt used for returning from stop mode.
(2) Sets the interrupt enable flag (I flag) to “1”.
(3) Clearing the protection and setting every-clock stop bit to “1” stops oscillation and causes the
processor to go into stop mode.
Operation
Settings and operation for entering stop mode are described here.
Figure 2.14.5. Example of stop mode set-up
All clocks off (stop mode)
b7
b0
1
(3) Canceling protect
Protect register [Address 000A
16
]
PRCR
Enables writing to system clock control registers 0 and 1
(addresses 0006
16
and 0007
16
)
1 : Write-enabled
(3) All clocks off (stop mode)
b7
b0
1
System clock control register 1 [Address 0007
16
]
CM1
0
0
0
0
Reserved bit
Must be set to “0”
All clock stop control bit
1 : All clocks off (stop mode)
Interrupt control register
SiTIC(i=0, 1)
SiRIC(i=0, 1)
TAiIC(i=0 to 4)
TBiIC(i=0 to 2)
b0
[Address 0051
16
, 0053
16
]
[Address 0052
16
, 0054
16
]
[Address 0055
16
to 0059
16
]
[Address 005A
16
to 005C
16
]
(1) Setting interrupt to cancel stop mode
Make sure that the interrupt priority
level of the interrupt which is used to
cancel the stop mode is higher than
the processor interrupt priority(IPL).
Interrupt priority level select bit
b7
INTiIC(i=0 to 2)
INTiIC(i=3 to 5)
b0
[Address 005D
16
to 005F
16
]
[Address 0047
16
to 0049
16
]
Make sure that the interrupt priority level of the
interrupt which is used to cancel the stop mode is
higher than the processor interrupt priority(IPL).
Interrupt priority level select bit
b7
0
Reserved bit
Must be set to “0”
System clock control register 0
[Address 0006
16
] CM0
(3) Setting operation clock after returning from stop mode
(When operating with X
IN
after returning)
On
Main clock (X
IN
-X
OUT
) stop bit
b7
0
b0
System clock select bit
X
IN
, X
OUT
As this register becomes setting mentioned above when
operating with X
IN
(count source of BCLK is X
IN
),
the user does not need to set it again.
0
System clock control register 0
[Address 0006
16
] CM0
X
CIN
-X
COUT
generation
System clock select bit
X
CIN
, X
COUT
Port X
C
select bit
b7
1
b0
As this register becomes setting mentioned above when operating with X
CIN
(count source of BCLK is X
CIN
), the user does not need to set it again.
When operating with X
IN
, set port Xc select bit to “1” before setting system clock
select bit to “1”. The both bits cannot be set at the same time.
1
(When operating with X
CIN
after returning)
(2) Interrupt enable flag (I flag) “1”