253
UART
M
i
t
s
u
M
S
b
i
s
3
M
h
0
I
C
i
m
2
R
i
1
O
c
r
8
C
o
c
o
G
M
m
p
r
P
u
t
u
T
e
r
p
R
s
o
U
S
I
N
G
L
E
-
C
H
I
P
1
6
-
B
I
T
C
M
O
O
E
Figure 2.5.5. UARTi-related registers (3)
UARTi transmit/receive control register 1
Symbol
UiC1(i=0,1)
Address
03A5
16
,
03AD
16
When reset
02
16
b7
b6
b5
b4
b3
b2
b1
b0
Bit name
Bit
symbol
W
R
Function
(During UART mode)
Function
(During clock synchronous serial
I/O mode)
TE
TI
RE
RI
Transmit enable bit
Receive enable bit
Receive complete flag
Transmit buffer empty
flag
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Reception disabled
1 : Reception enabled
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Reception disabled
1 : Reception enabled
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
Note: When using multiple pins to output the transfer clock, the following requirement must be met:
UART1 internal/external clock select bit (bit 3 at address 03A8
16
) = “0”.
UART transmit/receive control register 2
Symbol
UCON
Address
03B0
16
When reset
X0000000
2
b7
b6
0
b5
b4
b3
b2
b1
b0
Bit name
Bit
symbol
W
R
Function
(During UART mode)
Function
(During clock synchronous serial
I/O mode)
CLKMD0
CLKMD1
UART0 transmit
interrupt cause select bit
UART0 continuous receive
mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enable
UART1 continuous receive
mode enable bit
CLK/CLKS select bit 0
UART1 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : (TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : (TXEPT = 1)
0 : Normal mode
(CLK output is CLK1 only)
1 : Transfer clock output
from multiple pins
function selected
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
Must always be “0”
U0IRS
U1IRS
U0RRM
U1RRM
Invalid
Invalid
Invalid
CLK/CLKS select bit 1
(Note)
Valid when bit 5 = “1”
0 : Clock output to CLK1
1 : Clock output to CLKS1
Reserved bit
Must always be “0”
Must always be “0”
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.