參數(shù)資料
型號: M2V64S40DTP-8L
廠商: Mitsubishi Electric Corporation
英文描述: 64M Synchronous DRAM
中文描述: 6400同步DRAM
文件頁數(shù): 28/52頁
文件大?。?/td> 674K
代理商: M2V64S40DTP-8L
Apr. '99
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.2)
M2V64S20BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
28
DQM CONTROL
For x16, DQMU/L are dual function signals defined as the data mask for writes and the
output disable for reads. During writes, DQMU/L mask input data word by word. DQMU/L to
write mask latency is 0. During reads, DQMU/L force outputs to Hi-Z word by word. DQMU/L
to output Hi-Z latency is 2. DQML and DQMU control lower byte (DQ0-7), and upper byte
(DQ8-15), respectively.
DQM Function
CLK
Command
DQ0-7
Write
D0
D2
D3
DQML
READ
Q0
Q1
Q3
masked by DQML=H
disabled by DQMU=H
DQ8-15
D0
D2
D3
Q0
Q1
Q3
DQMU
D1
Q2
For x4/x8, DQM is a dual function signal defined as the data mask for writes and the
output disable for reads. During writes, DQM masks input data word by word. DQM to write
mask latency is 0. During reads, DQM forces output to Hi-Z word by word. DQM to output
Hi-Z latency is 2.
DQM Function
CLK
Command
DQ
Write
D0
D2
D3
DQM
READ
Q0
Q1
Q3
masked by DQM=H
disabled by DQM=H
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