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參數(shù)資料
| 型號： | M2V64S40DTP-8L |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 64M Synchronous DRAM |
| 中文描述： | 6400同步DRAM |
| 文件頁數(shù)： | 13/52頁 |
| 文件大?。?/td> | 674K |
| 代理商： | M2V64S40DTP-8L |
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Apr. '99
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.2)
M2V64S20BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
13
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a
SDRAM from damaged or malfunctioning.
1.Clock will be applied at power up along with power. Attempt to maintain CKE high,
DQM (x4,x8), DQMU/L (x16) high and NOP condition at the inputs along with power.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200us.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be
programmed by setting the mode register (MRS). The mode
register stores these data until the next MRS command, which
may be issued when both banks are in idle state. After tRSC
from a MRS command, the SDRAM is ready for new command.
R: Reserved for Future Use
FP: Full Page
BL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
BURST
LENGTH
BT= 0
1
2
4
8
R
R
R
FP
BT= 1
1
2
4
8
R
R
R
R
0
1
BURST
TYPE
SEQUENTIAL
INTERLEAVE
A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA1
BA0
0
0
WM
0
0
LTMODE
BT
BL
0
0
CL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
LATENCY
MODE
/CAS LATENCY
2
3
R
R
R
R
R
R
/CS
/RAS
/CAS
/WE
BA0,1 A11-A0
CLK
V
0
1
WRITE
MODE
BURST
SINGLE BIT
相關(guān)PDF資料 |
PDF描述 |
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| M2V64S40TP | 64M bit Synchronous DRAM |
| M2V64S40BTP | 64M bit Synchronous DRAM |
| M2V64S40BTP-10 | 64M bit Synchronous DRAM |
| M30201F6TFP | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30201 | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M2V64S40TP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M bit Synchronous DRAM |
| M2V64S4DTP-6 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M Synchronous DRAM |
| M2V64S4DTP-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M Synchronous DRAM |
| M2V64S4DTP-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M Synchronous DRAM |
| M2V64S50ETP | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:64M Single Data Rate Synchronous DRAM |
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