參數(shù)資料
型號(hào): M2V64S30DTP-6L
廠商: Mitsubishi Electric Corporation
英文描述: 64M Synchronous DRAM
中文描述: 6400同步DRAM
文件頁(yè)數(shù): 21/52頁(yè)
文件大?。?/td> 674K
代理商: M2V64S30DTP-6L
Apr. '99
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.2)
M2V64S20BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
21
[ Read Interrupted by Precharge ]
Burst read operation can be interrupted by precharge of
the same bank
. READ to PRE
interval is mini-mum 1 CLK. A PRE command to output disable latency is equivalent to
the /CAS Latency. As a result, READ to PRE interval determines valid data length to be
output. The figure below shows examples of BL=4.
Read Interrupted by Precharge (BL=4)
CLK
CL=3
Command
DQ
READ
PRE
Q0
Q1
Q2
Command
DQ
READ
PRE
Q0
CL=2
Command
DQ
READ
PRE
Q0
Q1
Q2
Command
DQ
READ
PRE
Q0
Command
DQ
READ PRE
Q0
Q1
Command
DQ
READ PRE
Q0
Q1
相關(guān)PDF資料
PDF描述
M2V64S30DTP-7 64M Synchronous DRAM
M2V64S30DTP-7L 64M Synchronous DRAM
M2V64S30DTP-8 64M Synchronous DRAM
M2V64S30DTP-8L 64M Synchronous DRAM
M2V64S30TP 64M bit Synchronous DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M2V64S30DTP-7 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M Synchronous DRAM
M2V64S30DTP-7L 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M Synchronous DRAM
M2V64S30DTP-8 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M Synchronous DRAM
M2V64S30DTP-8L 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M Synchronous DRAM
M2V64S30TP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M bit Synchronous DRAM