參數(shù)資料
型號: M2V64S30DTP-6L
廠商: Mitsubishi Electric Corporation
英文描述: 64M Synchronous DRAM
中文描述: 6400同步DRAM
文件頁數(shù): 20/52頁
文件大?。?/td> 674K
代理商: M2V64S30DTP-6L
Apr. '99
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.2)
M2V64S20BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
20
BURST INTERRUPTION
[ Read Interrupted by Read ]
Burst read operation can be interrupted by new read of any bank. Random column access
is allowed. READ to READ interval is minimum 1 CLK.
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of any bank. Random column access is
allowed. In this case, the DQ should be controlled adequately by using the DQM to prevent
the bus contention. The output is disabled automatically 1 cycle after WRITE assertion.
Read Interrupted by Read (BL=4, CL=3)
CLK
Command
A0-9
A10
BA0,1
DQ
Yi
Qai0
Qaj1 Qbk0 Qbk1
Qaj0
Qbk2
Qal0
Qal1
Qal2
Qal3
READ READ
READ
READ
Yj
Yk
Yl
0
0
0
0
00
10
00
01
A11
DQM control
Write control
Read Interrupted by Write (BL=4, CL=3)
CLK
Command
A0-9
A10
BA0,1
Q
READ
Yi
0
00
Qai0
Write
Yj
0
00
D
Daj0
Daj1
Daj2
Daj3
DQM(x4,x8)
DQMU/L(x16)
A11
相關(guān)PDF資料
PDF描述
M2V64S30DTP-7 64M Synchronous DRAM
M2V64S30DTP-7L 64M Synchronous DRAM
M2V64S30DTP-8 64M Synchronous DRAM
M2V64S30DTP-8L 64M Synchronous DRAM
M2V64S30TP 64M bit Synchronous DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M2V64S30DTP-7 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M Synchronous DRAM
M2V64S30DTP-7L 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M Synchronous DRAM
M2V64S30DTP-8 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M Synchronous DRAM
M2V64S30DTP-8L 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M Synchronous DRAM
M2V64S30TP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M bit Synchronous DRAM