參數(shù)資料
型號(hào)： M2V56D40ATP-10L
廠商： Mitsubishi Electric Corporation
英文描述： 256M Double Data Rate Synchronous DRAM
中文描述： 256M雙數(shù)據(jù)速率同步DRAM
文件頁(yè)數(shù)： 38/40頁(yè)
文件大?。?/td> 768K
代理商： M2V56D40ATP-10L
38
MITSUBISHI ELECTRIC
Mar. '02
MITSUBISHI LSIs
DDR SDRAM
(Rev.1.44)
M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10
M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L, -10
256M Double Data Rate Synchronous DRAM
The purpose of CLK suspend is power down. CKE is synchronous input except during the self-refresh mode. A
commands are ignored. From CKE=H to normal function, DLL recovery time is NOT required when the stable
CLK is supplied during the power down mode.
[Power DOWN]
/CLK
CLK
Power Down by CKE
Command
PRE
CKE
Command
ACT
CKE
Standby Power Down
NOP
NOP
Valid
NOP
NOP
Valid
Active Power Down
DM is defined as the data mask for write data. During writes, DM masks the input data cycle by cycle. Latency
of DM to write mask is 0.
[DM CONTROL]
DM Function(BL=8,CL=2)
Command
DQS
DQ
DM
WRITE
READ
D0 D1
D3 D4
D5 D6
D7
masked by DM=H
Don't Care
Q2
Q3
Q4
Q5
/CLK
CLK
Q0
Q1
Q6
tXPNR/tXPRD
相關(guān)PDF資料
PDF描述
M2V56D40ATP-75 256M Double Data Rate Synchronous DRAM
M2V56D40ATP-75A 256M Double Data Rate Synchronous DRAM
M2V56D40ATP-75AL 256M Double Data Rate Synchronous DRAM
M2V56D40ATP-75L 256M Double Data Rate Synchronous DRAM
M2V56D40ATP75A 256M Double Data Rate Synchronous DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M2V56D40ATP-75 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM
M2V56D40ATP75A 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM
M2V56D40ATP-75A 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM
M2V56D40ATP-75AL 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM
M2V56D40ATP-75L 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:256M Double Data Rate Synchronous DRAM
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