參數(shù)資料
型號: M29DW128F60ZA1F
廠商: 意法半導(dǎo)體
英文描述: 128 Mbit (16Mb x8 or 8Mb x16, Multiple Bank, Page, Boot Block) 3V Supply, Flash Memory
中文描述: 128兆位(16Mb的x8或和8Mb x16插槽,多行,頁,引導(dǎo)塊)3V電源,快閃記憶體
文件頁數(shù): 43/93頁
文件大小: 719K
代理商: M29DW128F60ZA1F
M29DW128F
6 Command Interface
43/93
Set Non-
Volatile Modify
Protection Bit
(5)
(6)
6
555
AA
2AA
55
555
60
(BA)/
NVMP
68
(BA)/
NVMP
48
(BA)/
NVMP
DQ0
Verify Non-
Volatile Modify
Protection Bit
4
555
AA
2AA
55
555
60
(BA)
/
NVMP
48
(BA)/
NVMP
DQ0
Clear Non-
Volatile Modify
Protection
Bits
(12)(13)(14)
6
555
AA
2AA
55
555
60
NVMP
60
(BA)/
NVMP
40
(BA)/
NVMP
DQ0
Set Lock-Down
bit
3
555
AA
2AA
55
555
78
Verify Lock-
Down bit
(15)
4
555
AA
2AA
55
555
58
BA
DQ1
Set Lock Bit
(7)
4
555
AA
2AA
55
555
48
BA
X1h
Clear Lock
Bit
(7)
4
555
AA
2AA
55
555
48
BA
X0h
Verify Lock Bit
4
555
AA
2AA
55
555
58
BA
DQ0
Set Standard
Protection
Mode
(5)(6)
6
555
AA
2AA
55
555
60
SL
68
SL
48
SL
DQ0
Verify Standard
Protection
Mode
(5)
4
555
AA
2AA
55
555
60
SL
DQ0
1.
Grey cells represent Read cycles. The other cells are Write cycles.
2.
SA Protection Group Address, BA Any address in the Block, BKA Bank Address, SL Standard Protection Mode Lock bit
Address, PL Password Protection Mode Lock Bit Address, PW Password Data,
PWA Password Address, RPW Password
Data Being Verified, NVMP Non-Volatile Modify Protection Bit Address, OW Extended Block Protection Bit Address,
X Don’t
Care. All values in the table are in hexadecimal.
3.
Addresses are described in
Table 17: Protection Command Addresses
.
4.
During Unlock and Command cycles, if the lower address bits are 555h or 2AAh then the address bits higher than A11
(except where BA is required) and data bits higher than DQ7 are Don't Care.
5.
A Reset Command must be issued to return to the Read mode.
The 4
th
Bus Write cycle programs a protection bit (Extended Block Protection bit, Password Protection Mode Lock bit,
Standard Protection Mode Lock bit, and a block NVMP bit). The 5
th
and 6
th
cycles verify that the bit has been successively
programmed when DQ0=1. If DQ0=0 in the 6
th
cycle, the program command must be issued again and verified again. A
100μs delay is required between the 4th and the 5th cycle.
6.
7.
Data is latched on the rising edge of W.
8.
The entire command sequence must be entered for each portion of the password.
9.
The command sequence returns FFh if the Password Protection Mode locking bit is set.
10. The password is written over four consecutive cycles, at addresses [0-3]
11. A 2μs timeout is required between any two portions of the password.
12. A 10ms delay is required between the 4th and the 5th cycle.
13. A 12ms timeout is required between cycles 4 and 5.
Command
L
Bus Operations
(1)(2)(3)(4)
1st
2nd
3rd
4th
5th
6th
7th
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
Add
Data
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