參數(shù)資料
型號: M29DW128F60NF6F
廠商: 意法半導體
英文描述: 128 Mbit (16Mb x8 or 8Mb x16, Multiple Bank, Page, Boot Block) 3V Supply, Flash Memory
中文描述: 128兆位(16Mb的x8或和8Mb x16插槽,多行,頁,引導塊)3V電源,快閃記憶體
文件頁數(shù): 20/93頁
文件大小: 719K
代理商: M29DW128F60NF6F
3 Bus operations
M29DW128F
20/93
Table 5.
Block Protection, 8-bit Mode
Table 6.
Bus Operations, 16-bit Mode
Table 7.
Read Electronic Signature, 16-bit Mode
Operation
(1)
1.
X = V
IL
or V
IH
.
BKA Bank Address, BA any Address in the Block.
E
G
W
RP
V
PP
/
WP
Address Inputs
(2)
2.
Data Inputs/Outputs
A22-
A12
A11-
A10
A9
A8 A7
A6
A5-
A4
A3-
A2
A1
A0
DQ15A
-1
DQ14-
DQ8
DQ7-DQ0
Verify
Extended
Block
Protection
Indicator
(bits DQ6,
DQ7)
V
IL
V
IL
V
IH
V
IH
V
IH
BA
X
V
ID
X
X
V
IL
X
V
IL
V
IH
V
IH
X
Hi-Z
80h
(Customer
Lockable)
C0h
(Customer
Locked)
(3)
3.
This indicates the protection status of the second section of the Extended Block; the first section of the Extended Block
being always Factory Locked.
Verify Block
Protection
Status
BKA
V
IL
V
IL
V
IL
X
01h
(protected)
00h
(unprotected)
Temporary
Block
Unprotect
(4)
4.
The RP pin unprotects all the blocks that have been previously protected using a High Voltage protection Technique.
X
X
X
V
ID
X
Valid
Data Input
Operation
(1)
1.
X = V
IL
or V
IH
.
E
G
W
RP
V
PP
/
WP
Address Inputs
Data Inputs/Outputs
A22-A0
DQ15A-1, DQ14-DQ0
Bus Read
V
IL
V
IL
V
IH
V
IH
V
IH
Cell Address
Data Output
Bus Write
V
IL
V
IH
V
IL
V
IH
V
IH
Command Address
Data Input
Output Disable
X
V
IH
V
IH
V
IH
V
IH
X
Hi-Z
Standby
V
IH
X
X
V
IH
V
IH
X
Hi-Z
Read Cycle
(1)
1.
X = V
IL
or V
IH
.
E
G
W
Address Inputs
Data Inputs/Outputs
A22-
A10
A9
A8
A7-
A6
A5-
A4
A3
A2
A1
A0
DQ15A-1, DQ14-DQ0
Manufacturer Code
V
IL
V
IL
V
IH
X
V
ID
X
V
IL
X
V
IL
V
IL
V
IL
V
IL
0020h
Device Code (Cycle 1)
V
IL
V
IL
V
IL
V
IL
V
IH
227Eh
Device Code (Cycle 2)
V
IH
V
IH
V
IH
V
IL
2220h
Device Code (Cycle 3)
V
IH
V
IH
V
IH
V
IH
2200h
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