參數(shù)資料
型號(hào): M25PX32-VMF6F
廠商: 意法半導(dǎo)體
元件分類: DRAM
英文描述: 4 Mbit Uniform Sector, Serial Flash Memory
中文描述: 4兆位統(tǒng)一部門,串行閃存
文件頁數(shù): 46/63頁
文件大小: 394K
代理商: M25PX32-VMF6F
Instructions
M25PX32
46/63
6.17
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write
Enable (WREN) instruction must previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code on Serial Data input (DQ0). Chip Select (S) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in
Figure 25
.
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S)
is driven High, the self-timed Bulk Erase cycle (whose duration is t
BE
) is initiated. While the
Bulk Erase cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk
Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
The Bulk Erase (BE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits are
0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected.
Figure 25.
Bulk Erase (BE) instruction sequence
C
DQ0
AI13743
S
2
1
3
4
5
6
7
0
Instruction
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M25PX32-VMF6FBA 制造商:Micron Technology Inc 功能描述:AUTOMOTIVE - Tape and Reel
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