參數資料
型號: M25PE40
廠商: 意法半導體
元件分類: DRAM
英文描述: 4 Mbit Uniform Sector, Serial Flash Memory
中文描述: 4兆位統(tǒng)一部門,串行閃存
文件頁數: 42/60頁
文件大?。?/td> 315K
代理商: M25PE40
Power-up and Power-down
M25PE40
42/60
7
Power-up and Power-down
At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on V
CC
) until V
CC
reaches the correct value:
V
CC
(min) at Power-up, and then for a further delay of t
VSL
V
SS
at Power-down
A safe configuration is provided in
Section 3: SPI modes
.
To avoid data corruption and inadvertent write operations during power up, a Power On
Reset (POR) circuit is included. The logic inside the device is held reset while V
CC
is less
than the Power On Reset (POR) threshold voltage, V
WI
– all operations are disabled, and
the device does not respond to any instruction.
Moreover, the device ignores all Write Enable (WREN), Page Write (PW), Page Program
(PP), Page Erase (PE) and Sector Erase (SE) instructions until a time delay of t
PUW
has
elapsed after the moment that V
CC
rises above the V
WI
threshold. However, the correct
operation of the device is not guaranteed if, by this time, V
CC
is still below V
CC
(min). No
Write, Program or Erase instructions should be sent until the later of:
t
PUW
after V
CC
passed the V
WI
threshold
t
VSL
after V
CC
passed the V
CC
(min) level
These values are specified in
Table 11
If the delay, t
VSL
, has elapsed, after V
CC
has risen above V
CC
(min), the device can be
selected for READ instructions even if the t
PUW
delay is not yet fully elapsed.
As an extra protection, the Reset (Reset) signal could be driven Low for the whole duration
of the Power-up and Power-down phases.
At Power-up, the device is in the following state:
The device is in the Standby Power mode (not the Deep Power-down mode)
The Write Enable Latch (WEL) bit is reset
The Write In Progress (WIP) bit is reset
The Lock Registers are reset (Write Lock bit, Lock Down bit) = (0, 0)
Normal precautions must be taken for supply rail decoupling, to stabilize the V
CC
supply.
Each device in a system should have the V
CC
rail decoupled by a suitable capacitor close to
the package pins. (Generally, this capacitor is of the order of 100 nF).
At Power-down, when V
CC
drops from the operating voltage, to below the Power On Reset
(POR) threshold voltage, V
WI
, all operations are disabled and the device does not respond
to any instruction. (The designer needs to be aware that if a Power-down occurs while a
Write, Program or Erase cycle is in progress, some data corruption can result.)
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