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參數(shù)資料
| 型號： | M25P16-VMN3TP |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | 4 Mbit Uniform Sector, Serial Flash Memory |
| 中文描述： | 4兆位統(tǒng)一部門，串行閃存 |
| 文件頁數(shù)： | 10/55頁 |
| 文件大?。?/td> | 335K |
| 代理商： | M25P16-VMN3TP |
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SPI modes
M25P16
10/55
3
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
CPOL=0, CPHA=0
CPOL=1, CPHA=1
●
●
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in
Figure 5
, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
●
●
Figure 4.
Bus master and memory devices on the SPI bus
1.
Figure 4
shows an example of three devices connected to an MCU, on an SPI bus. Only one
device is selected at a time, so only one device drives the Serial Data Output (Q) line at a
time, the other devices are high impedance. Resistors R (represented in
Figure 4
) ensure
that the M25P16 is not selected if the Bus Master leaves the S line in the high impedance
state. As the Bus Master may enter a state where all inputs/outputs are in high impedance
at the same time (for example, when the Bus Master is reset), the clock line (C) must be
connected to an external pull-down resistor so that, when all inputs/outputs become high
impedance, the S line is pulled High while the C line is pulled Low (thus ensuring that S and
C do not become High at the same time, and so, that the t
SHCH
requirement is met). The
typical value of R is 100 k
, assuming that the time constant R*C
p
(C
p
= parasitic
capacitance of the bus line) is shorter than the time during which the Bus Master leaves the
SPI bus in high impedance.
The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
AI12836b
SPI Bus Master
SPI Memory
Device
SDO
SDI
SCK
C
Q
D
S
SPI Memory
Device
C
Q
D
S
SPI Memory
Device
C
Q
D
S
CS3
CS2 CS1
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
W
HOLD
W
HOLD
W
HOLD
R
R
R
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
V
SS
V
SS
R
相關(guān)PDF資料 |
PDF描述 |
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| M25P16-VMN6G | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25P16-VMN6P | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25P16-VMN6TG | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25P16-VMP3G | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25P16-VMP3P | 4 Mbit Uniform Sector, Serial Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M25P16-VMN3TP/4 | 功能描述:IC FLASH 16MBIT 75MHZ 8SOIC RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:Forté™ 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標(biāo)準(zhǔn)包裝:136 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步，DDR II 存儲容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應(yīng)商設(shè)備封裝:165-CABGA（13x15） 包裝:托盤 其它名稱:71P71804S200BQ |
| M25P16-VMN3TPB | 功能描述:IC SRL FLSH 16MBIT 3V 75MHZ S08N RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:Forté™ 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 存儲容量:4.5M（256K x 18） 速度:133MHz 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x20） 包裝:托盤 |
| M25P16-VMN3YPB | 制造商:Micron Technology Inc 功能描述:AUTOMOTIVE, SERIAL NOR, 16MB - Trays 制造商:Micron Technology Inc 功能描述:IC FLASH 16MBIT 75MHZ 8SO |
| M25P16VMN6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:512 Kbit to 32 Mbit, Low Voltage, Serial Flash Memory With 40 MHz or 50 MHz SPI Bus Interface |
| M25P16-VMN6 | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:16 Mbit, serial Flash memory, 75 MHz SPI bus interface |
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