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參數(shù)資料
| 型號： | M2006-04-622.0800LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| 封裝： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 417K |
| 代理商： | M2006-04-622.0800LF |
M2006-04 Datasheet Rev 0.1
Revised 29Apr2003
Integ r ated Circuit Systems , Inc. ● Comm unications Modules ● www.icst.com ● tel (508) 852-5400
M2006-04
VCSO BASED FREQUENCY TRANSLATOR
Prelimina r y Inf o r m ation
GENERAL DESCRIPTION
The M2006-04 is a VCSO (Voltage Controlled SAW
Oscillator) based clock generator
PLL designed for clock frequency
translation and jitter attenuation.
It features serially programmable
configuration of PLL frequency
translation ratios, including FEC
and inverse FEC. The device is
similar to the M2006-11 (with compatible pins and
functions) except that it omits automatic protection
switching (APS) and phase compensation (APC).
FEATURES
◆ Integrated SAW (surface acoustic wave) delay line
◆ VCSO frequency from 300 to 700MHz
(Specify center frequency at time of order)
◆ Low phase jitter 0.5ps rms, typical (12kHz to 20MHz or
50kHz to 80MHz)
◆ Similar to the M2006-11 (and pin-compatible), but omits
APS (automatic protection switching) and APC
◆ Ideal for use with an unstable reference
(that which results in phase detector jitter beyond 2 ns
under normal operating conditions)
◆ Narrow Bandwidth (NBW) control pin provides manual
PLL control (set high for narrow bandwidth)
◆ Clock Add/Drop feature enables data FIFO centering
◆ Universal differential reference inputs support LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
◆ Power-up frequency translation ratio of x32 useful for
19.44MHz input and 155.52 or 622.08MHz output
◆ Single 3.3V power supply
◆ Small 9 x 9 mm SMT (surface mount) package
PIN ASSIGNMENT (9 x 9 mm SMT)
Figure 1: Pin Assignment
SIMPLIFIED BLOCK DIAGRAM
Figure 2: Simplified Block Diagram
Example Input / Output Frequency Combinations
Input
Clock
(MHz)
VCSO
Freq 1
(MHz)
Note 1: Specify VCSO center frequency at time of order
Output
Freq
(MHz)
Application
19.44
622.08
OC-12/48
155.52
19.53125
625.00
156.25
Gigabit Ethernet
Using Power-up PLL Ratio
M2006-04 VCSO Based Frequency Translator
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| M2006-12-669.1281 | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| M2006-12I-669.6429 | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| M2006-12-644.5313LF | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| M2006-12-670.8386 | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M2006-04-625.0000 | 制造商:Integrated Device Technology Inc 功能描述:9X9 LCC(LEAD FREE) - Bulk 制造商:Integrated Device Technology Inc 功能描述:FREQUENCY TRANSLATOR |
| M2006-04-625.0000T | 功能描述:時(shí)鐘合成器/抖動清除器 FREQUENCY TRANSLATOR RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| M2006099 | 制造商:TURCK Inc 功能描述:WIRE AND CABLE |
| M2006-11-622.0800 | 制造商:Ics 功能描述:PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), 36 Pin Ceramic LCC |
| M2006-12 | 制造商:ICS 制造商全稱:ICS 功能描述:VCSO BASED FEC CLOCK PLL / HITLESS SWITCHING OPTION |
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