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參數(shù)資料
| 型號(hào)： | M2006-04-622.0800LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| 封裝： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件頁(yè)數(shù)： | 11/12頁(yè) |
| 文件大小： | 417K |
| 代理商： | M2006-04-622.0800LF |
M2006-04 Datasheet Rev 0.1
8 of 12
Revised 29Apr2003
Integr ate d Circuit Systems , In c. ● Comm unication s Modules ● www.icst.com ● tel (508) 852-5400
M2006-04
VCSO BASED FREQUENCY TRANSLATOR
Preliminar y In f o r m atio n
Add / Drop Clock
The ADD_CLK and DROP_CLK inputs increment or
decrement the M (feedback) divider on the rising edge
of the Add or Drop clock for one phase detector cycle.
This results in a momentary increase or decrease in
output frequency and an extra or missing VCSO output
clock cycle (clock slip) relative to the input reference
clock.
The ADD_CLK (pin 30) and DROP_CLK (pin 31) inputs are
intended to be used for pointer realignment in the data
channel FIFO register. The assertion of either pin
imparts a single VCSO cycle slip over time. The rate at
which the cycle occurs is determined by the loop filter
bandwidth, which is influenced by the external loop filter
components selection (see Table 8, External Loop
Adding One Clock Cycle
When ADD_CLK is transitioned from low to high, one extra
clock will be output by the VCSO relative to the
reference input. This is accomplished by incrementing
the feedback divider (M Divider) by one count for one
phase detector cycle period (one R Divider output
cycle).
This incrementing of the feedback divider creates an
immediate error at the phase detector input equal to
one VCSO clock cycle. In the process of relocking the
phase of the M Divider output to the R Divider output,
the PLL forces the VCSO frequency to slightly increase
(several ppm) and then decrease once locked. The net
effect is a single “cycle slip” of the VCSO over several
milliseconds. A VCSO frequency of 622.08MHz
represents a cycle time of 1.6 nsec, which is the phase
error imparted on the phase detector with one ADD_CLK
command.
Dropping One Clock Cycle
The DROP_CLK pin works the same way, except that
when this pin transitions from to low to high, the
feedback counter is decremented by one count which
subtracts one VCSO output clock over time.
How Assertions Affect the Add / Drop Functions
Both ADD_CLK and DROP_CLK modify the M Divider
following the next rising edge of the reference clock into
the phase detector (the R Divider output). Only one
ADD_CLK
assertion or DROP_CLK assertion can be made
per phase detector clock cycle. Additional assertions
during a given phase detector cycle will be ignored.
Additional assertions prior to phase detector
realignment will accumulate as additional phase
detector error, and will cause further VCSO frequency
offset.
How Output Divider Affects the Add / Drop Functions
The divider block (P Divider) between the VCSO output
and the FOUT1 clock output pair also influences the effect
of ADD_CLK and DROP_CLK assertions relative to the FOUT1
output. When P1 is low (forces P Divider = 1) the ADD_CLK
or DROP_CLK pin will add or subtract one entire clock
cycle upon a single assertion (this is always true for the
FOUT0
output clock pair). When P1 is high (forces
P Divider = 4) the ADD_CLK or DROP_CLK pin will add or
subtract one quarter of a clock cycle upon a single
Add / Drop Functions
Pa X = Don't care; = Rising Edge Transition
ADD_CLK
DROP_CLK Conditions
X
Adds one extra clock cycle to the VCSO clock output, over time, when asserted.
X
Subtracts one clock cycle to the VCSO clock output, over time, when asserted.
Table 9: Add / Drop Functions
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| M2006-04-625.0000 | 制造商:Integrated Device Technology Inc 功能描述:9X9 LCC(LEAD FREE) - Bulk 制造商:Integrated Device Technology Inc 功能描述:FREQUENCY TRANSLATOR |
| M2006-04-625.0000T | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 FREQUENCY TRANSLATOR RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| M2006099 | 制造商:TURCK Inc 功能描述:WIRE AND CABLE |
| M2006-11-622.0800 | 制造商:Ics 功能描述:PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), 36 Pin Ceramic LCC |
| M2006-12 | 制造商:ICS 制造商全稱:ICS 功能描述:VCSO BASED FEC CLOCK PLL / HITLESS SWITCHING OPTION |
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