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參數(shù)資料
| 型號： | M2006-04-622.0800LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| 封裝： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 417K |
| 代理商： | M2006-04-622.0800LF |
M2006-04 Datasheet Rev 0.1
2 of 12
Revised 29Apr2003
Integr ate d Circuit Systems , In c. ● Comm unication s Modules ● www.icst.com ● tel (508) 852-5400
M2006-04
VCSO BASED FREQUENCY TRANSLATOR
Preliminar y In f o r m atio n
PIN DESCRIPTIONS
Number
Name
I/O
Configuration
Description
1, 2, 3, 10, 14, 26
GND
Ground
Power supply ground connections.
4
9
OP_IN
nOP_IN
Input
External loop filter connections. See Figure 5,
5
8
nOP_OUT
OP_OUT
Output
6
7
nVC
VC
Input
11, 19, 33
VCC
Power
Power supply connection, connect to +3.3V.
12
13
FOUT1
nFOUT1
Output
No internal terminator
Clock output pairs. Differential LVPECL.
15
16
FOUT0
nFOUT0
17
P1
Input
Internal pull-down resistor1
Note 1: For typical values of internal pull-down and pull-up resistors, see
P Divider control. LVCMOS/LVTTL. For P1:
Logic 1 sets divider to 4
Logic 0 sets divider to 1
See Table 5, P Divider Selection, on pg. 3
18
20
21
S_CLOCK
S_DATA
S_LOAD
Input
Internal pull-down resistors1
Serial input mode selection. LVCMOS/LVTTL.
See Table 6, Serial Mode Function, on pg. 5 for
how these three pins are used in combination.
22
29
REF_SEL1
REF_SEL0
Input
Internal pull-down resistors1
Reference clock input selection. LVCMOS/LVTTL.
See Table 3, Reference Clock Input Selection,
on pg. 3
23
nDIF_REF0
Input
Internal pull-up resistor1
Reference clock input pair 0.
Differential LVPECL or LVDS.
24
DIF_REF0
Internal pull-down resistor1
25
REF_CLK
Input
Internal pull-down resistor1
Reference clock input. LVCMOS/LVTTL.
27
nDIF_REF1
Input
Internal pull-up resistor1
Reference clock input pair 1.
Differential LVPECL or LVDS.
28
DIF_REF1
Internal pull-down resistor1
30
ADD_CLK
Input
Internal pull-down resistor1
Increases M divider count by 1 for one phase
detector cycle, which adds one extra VCSO clock
cycle over time (clock slip). LVCMOS/LVTTL.
31
DROP_CLK
Decreases M divider count by 1 for one phase
detector cycle, which removes one VCSO clock
cycle over time (clock slip). LVCMOS/LVTTL. See
Table 9, Add / Drop Functions,
on pg. 8.
32
NBW
Input
Internal pull-up resistor1
Narrow Bandwidth enable. LVCMOS/LVTTL:
Logic 1 - Narrow loop bandwidth, R
IN set to 2M
.
Logic 0 - Wide (normal) bandwidth, R
IN set to 50k
.
34, 35, 36
DNC
Do Not Connect.
Table 2: Pin Descriptions
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M2006-04-625.0000 | 制造商:Integrated Device Technology Inc 功能描述:9X9 LCC(LEAD FREE) - Bulk 制造商:Integrated Device Technology Inc 功能描述:FREQUENCY TRANSLATOR |
| M2006-04-625.0000T | 功能描述:時鐘合成器/抖動清除器 FREQUENCY TRANSLATOR RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| M2006099 | 制造商:TURCK Inc 功能描述:WIRE AND CABLE |
| M2006-11-622.0800 | 制造商:Ics 功能描述:PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), 36 Pin Ceramic LCC |
| M2006-12 | 制造商:ICS 制造商全稱:ICS 功能描述:VCSO BASED FEC CLOCK PLL / HITLESS SWITCHING OPTION |
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