參數(shù)資料
型號： M1AGLE3000V5-FG484
廠商： Microsemi SoC
文件頁數(shù)： 65/166頁
文件大?。?/td> 0K
描述： IC FPGA 1KB FLASH 3M 484-FBGA
標(biāo)準(zhǔn)包裝： 60
系列： IGLOOe
邏輯元件/單元數(shù)： 75264
RAM 位總計(jì)： 516096
輸入/輸出數(shù)： 341
門數(shù)： 3000000
電源電壓： 1.425 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 484-BGA
供應(yīng)商設(shè)備封裝： 484-FPBGA（23x23）
Revision 13
5-1
5 – Datasheet Information
List of Changes
The following table lists critical changes that were made in each revision of the IGLOOe datasheet.
Revision
Changes
Page
Revision 13
(December 2012)
The "IGLOOe Ordering Information" section has been updated to mention "Y" as "Blank"
mentioning "Device Does Not Include License to Implement IP Based on the
Cryptography Research, Inc. (CRI) Patent Portfolio" (SAR 43176).
Also added the missing heading ’Supply Voltage’ under V2.
CCC/PLL Specification referring the reader to SmartGen was revised to refer instead to
the online help associated with the core (SAR 42568).
Live at Power-Up (LAPU) has been replaced with ’Instant On’.
NA
Revision 12
(September 2012)
The "Security" section was modified to clarify that Microsemi does not support
read-back of programmed data.
Libero Integrated Design Environment (IDE) was changed to Libero System-on-Chip
(SoC) throughout the document (SAR 40272).
N/A
Revision 11
(August 2012)
The drive strength, IOL, and IOH value for 3.3 V GTL and 2.5 V GTL was changed from
25 mA to 20 mA in the following tables (SAR 37180):
Also added note stating "Output drive strength is below JEDEC specification." for Tables 2-
25, 2-26, and 2-28.
Additionally, the IOL and IOH values for 3.3 V GTL+ and 2.5 V GTL+ were corrected
from 51 to 35 (for 3.3 V GTL+) and from 40 to 33 (for 2.5 V GTL+) in table Table 2-21
(SAR 39713).
revised so that the maximum is 3.6 V for all listed values of VCCI (SAR 37183).
The following sentence was removed from the "VMVx I/O Supply Voltage (quiet)"
section in the "Pin Descriptions and Packaging" section: "Within the package, the VMV
plane is decoupled from the simultaneous switching noise originating from the output
buffer VCCI domain" and replaced with “Within the package, the VMV plane biases the
input stage of the I/Os in the I/O banks” (SAR 38318). The datasheet mentions that
"VMV pins must be connected to the corresponding VCCI pins" for an ESD
enhancement.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M1AGLE3000V5-FG484I 功能描述:IC FPGA 1KB FLASH 3M 484-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:IGLOOe 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
M1AGLE3000V5-FG896 功能描述:IC FPGA 1KB FLASH 3M 896-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:IGLOOe 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
M1AGLE3000V5-FG896ES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
M1AGLE3000V5-FG896I 功能描述:IC FPGA 1KB FLASH 3M 896-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:IGLOOe 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
M1AGLE3000V5-FG896PP 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
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