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    參數(shù)資料
    

    


    


    
型號(hào)：
M1A3PE3000-1FG484I

    

    
廠商：
Microsemi SoC

    

    
文件頁數(shù)：
1/162頁

    

    
文件大?。?/td>
0K

    

    
描述：
IC FPGA 1KB FLASH 3M 484-FBGA

    

    
標(biāo)準(zhǔn)包裝：
40

    

    
系列：
ProASIC3E

    

    
RAM 位總計(jì)：
516096
    		

    

    
輸入/輸出數(shù)：
341
    		

    

    
門數(shù)：
3000000
    		

    

    
電源電壓：
1.425 V ~ 1.575 V
    		

    

    
安裝類型：
表面貼裝
    		

    

    
工作溫度：
-40°C ~ 85°C
    		

    

    
封裝/外殼：
484-BGA
    		

    

    
供應(yīng)商設(shè)備封裝：
484-FPBGA（23x23）
    		

    

    

    

	
    
    
    

    
    
	
    January 2013
    I
     2013 Microsemi Corporation
    ProASIC3E Flash Family FPGAs
    with Optional Soft ARM Support
    Features and Benefits
    High Capacity
     600 k to 3 Million System Gates
     108 to 504 kbits of True Dual-Port SRAM
     Up to 620 User I/Os
    Reprogrammable Flash Technology
     130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
    Process
     Instant On Level 0 Support
     Single-Chip Solution
     Retains Programmed Design when Powered Off
    On-Chip User Nonvolatile Memory
     1 kbit of FlashROM with Synchronous Interfacing
    High Performance
     350 MHz System Performance
     3.3 V, 66 MHz 64-Bit PCI
    In-System Programming (ISP) and Security
     ISP Using On-Chip 128-Bit Advanced Encryption Standard
    (AES) Decryption via JTAG (IEEE 1532–compliant)
     FlashLock Designed to Secure FPGA Contents
    Low Power
     Core Voltage for Low Power
     Support for 1.5-V-Only Systems
     Low-Impedance Flash Switches
    High-Performance Routing Hierarchy
     Segmented, Hierarchical Routing and Clock Structure
     Ultra-Fast Local and Long-Line Network
     Enhanced High-Speed, Very-Long-Line Network
     High-Performance, Low-Skew Global Network
     Architecture Supports Ultra-High Utilization
    Pro (Professional) I/O
     700 Mbps DDR, LVDS-Capable I/Os
     1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
     Bank-Selectable I/O Voltages—up to 8 Banks per Chip
     Single-Ended
    I/O
    Standards:
    LVTTL,
    LVCMOS
    3.3 V /
    2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS
    2.5 V / 5.0 V Input
     Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
    M-LVDS
     Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL
    2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3
    Class I and II
     I/O Registers on Input, Output, and Enable Paths
     Hot-Swappable and Cold Sparing I/Os
     Programmable Output Slew Rate and Drive Strength
     Programmable Input Delay
     Schmitt Trigger Option on Single-Ended Inputs
     Weak Pull-Up/-Down
     IEEE 1149.1 (JTAG) Boundary Scan Test
     Pin-Compatible Packages across the ProASIC3E Family
    Clock Conditioning Circuit (CCC) and PLL
     Six CCC Blocks, Each with an Integrated PLL
     Configurable Phase-Shift, Multiply/Divide, Delay Capabilities
    and External Feedback
     Wide Input Frequency Range (1.5 MHz to 350 MHz)
    SRAMs and FIFOs
     Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,
    and ×18 organizations available)
     True Dual-Port SRAM (except ×18)
     24 SRAM and FIFO Configurations with Synchronous Operation
    up to 350 MHz
    ARM Processor Support in ProASIC3E FPGAs
     M1 ProASIC3E Devices—Cortex-M1 Soft Processor Available
    with or without Debug
    Table 1-1  ProASIC3E Product Family
    ProASIC3E Devices
    A3PE600
    A3PE1500
    A3PE3000
    Cortex-M1 Devices 1
    M1A3PE1500
    M1A3PE3000
    System Gates
    600,000
    1,500,000
    3,000,000
    VersaTiles (D-flip-flops)
    13,824
    38,400
    75,264
    RAM Kbits (1,024 bits)
    108
    270
    504
    4,608-Bit Blocks
    24
    60
    112
    FlashROM Kbits
    11
    1
    Secure (AES) ISP
    Yes
    CCCs with Integrated PLLs2
    66
    6
    VersaNet Globals3
    18
    I/O Banks
    88
    8
    Maximum User I/Os
    270
    444
    620
    Package Pins
    PQFP
    FBGA
    PQ208
    FG256, FG484
    PQ208
    FG484, FG676
    PQ208
    FG324
    , FG484, FG896
    Notes:
    1. Refer to the Cortex-M1 product brief for more information.
    2. The PQ208 package supports six CCCs and two PLLs.
    3. Six chip (main) and three quadrant global networks are available.
    4. For devices supporting lower densities, refer to the ProASIC3 Flash Family FPGAs datasheet.
    Revision 13
    
    
    
    
    
    


    


    

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    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
M1A3PE3000-1FG896
功能描述:IC FPGA 1KB FLASH 3M 896-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3E 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs
	Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）

    

    
M1A3PE3000-1FG896ES
 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs

    

    
M1A3PE3000-1FG896I
功能描述:IC FPGA 1KB FLASH 3M 896-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3E 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）

    

    
M1A3PE3000-1FG896PP
 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs

    

    
M1A3PE3000-1FGG324
功能描述:IC FPGA 1KB FLASH 3M 324-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3E 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs
	Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）

    

    
    
    
    
	
    	
    
    
     
     
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