Revision 13 2-25 Table 2-25 Summary of I/O Timing Characteristics—Software Default Settings " />
參數(shù)資料
型號: M1AGLE3000V5-FG484
廠商: Microsemi SoC
文件頁數(shù): 100/166頁
文件大?。?/td> 0K
描述: IC FPGA 1KB FLASH 3M 484-FBGA
標準包裝: 60
系列: IGLOOe
邏輯元件/單元數(shù): 75264
RAM 位總計: 516096
輸入/輸出數(shù): 341
門數(shù): 3000000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 484-BGA
供應商設備封裝: 484-FPBGA(23x23)
IGLOOe Low Power Flash FPGAs
Revision 13
2-25
Table 2-25 Summary of I/O Timing Characteristics—Software Default Settings
Std. Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI (per standard)
I/O Standard
D
rive
S
tre
ng
th
(mA)
Eq
ui
va
le
nt
Sof
twar
eDefau
lt
D
rive
S
tre
ng
th
Op
tio
n
1 (m
A)
Slew
Rate
C
ap
a
citive
L
o
a
d
(pF
)
Ex
tern
al
Re
sistor
(
)
t DO
U
T
(ns)
t DP
(ns)
t DI
N
(ns)
t PY
(ns)
t PYS
(ns)
t EOUT
(ns)
t ZL
(ns)
t ZH
(ns)
t LZ
(ns)
t HZ
(ns)
t ZL
S
(ns)
t ZH
S
(n
s)
Un
it
s
3.3 V LVTTL /
3.3 V LVCMOS
12
High 5
0.97 2.12 0.18 1.08 1.34 0.66 2.17 1.69 2.71 3.08 5.76 5.28 ns
3.3 V LVCMOS
Wide Range1, 2
100 A
12
High
5
0.972.960.181.421.840.662.982.283.864.366.585.87 ns
2.5 V LVCMOS
12
High
5
.097 2.15 0.18 1.31 1.41 0.66 2.20 1.85 2.78 2.98 5.80 5.45 ns
1.8 V LVCMOS
12
High 5
0.97 2.37 0.18 1.27 1.59 0.66 2.42 2.03 3.07 3.57 6.02 5.62 ns
1.5 V LVCMOS
12
High 5
0.97 2.69 0.18 1.47 1.77 0.66 2.75 2.30 3.24 3.67 6.35 5.89 ns
3.3 V PCI
Per
PCI
spec
High 10 25 3 0.97 2.38 0.18 0.96 1.42 0.66 2.43 1.80 2.72 3.08 6.03 5.39 ns
3.3 V PCI-X
Per
PCI-X
spec
High 10 25 3 0.97 2.38 0.19 0.92 1.34 0.66 2.43 1.80 2.72 3.08 6.03 5.39 ns
3.3 V GTL
204
High 10
25 0.97 1.78 0.19 2.35
0.66 1.80 1.78
5.39 5.38 ns
2.5 V GTL
204
High 10
25 0.97 1.85 0.19 1.98
0.66 1.89 1.82
5.49 5.42 ns
3.3 V GTL+
35
High 10
25 0.97 1.80 0.19 1.32
0.66 1.84 1.77
5.44 5.36 ns
2.5 V GTL+
33
High 10
25 0.97 1.92 0.19 1.26
0.66 1.96 1.80
5.56 5.40 ns
HSTL (I)
8
High 20
50 0.97 2.67 0.18 1.72
0.66 2.72 2.67
6.32 6.26 ns
HSTL (II)
15
High 20
25 0.97 2.55 0.18 1.72
0.66 2.60 2.34
6.20 5.93 ns
SSTL2 (I)
15
High 30
50 0.97 1.86 0.19 1.12
0.66 1.90 1.68
5.50 5.28 ns
SSTL2 (II)
18
High 30
25 0.97 1.89 0.19 1.12
0.66 1.93 1.62
5.53 5.22 ns
SSTL3 (I)
14
High 30
50 0.97 2.00 0.19 1.06
0.66 2.04 1.67
5.64 5.27 ns
SSTL3 (II)
21
High 30
25 0.97 1.81 0.19 1.06
0.66 1.85 1.55
5.45 5.14 ns
LVDS
24
High
– 0.97 1.73 0.19 1.62
––––––
––
ns
LVPECL
24
High
– 0.97 1.65 0.18 1.42
––––––
––
ns
Notes:
1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is
±100 A. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the
IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
3. Resistance is used to measure I/O propagation delays as defined in PCI Specifications. See Figure 2-12 on page 2-49 for
connectivity. This resistor is not required during normal operation.
4. Output drive strength is below JEDEC specification.
5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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